1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <asm/io.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/dma.h>
13 #include <asm/mach-imx/hab.h>
14 #include <asm/mach-imx/rdc-sema.h>
15 #include <asm/arch/imx-rdc.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/arch/crm_regs.h>
18 #include <dm.h>
19 #include <env.h>
20 #include <imx_thermal.h>
21 #include <fsl_sec.h>
22 #include <asm/setup.h>
23 #include <linux/delay.h>
24
25 #define IOMUXC_GPR1 0x4
26 #define BM_IOMUXC_GPR1_IRQ 0x1000
27
28 #define GPC_LPCR_A7_BSC 0x0
29 #define GPC_LPCR_M4 0x8
30 #define GPC_SLPCR 0x14
31 #define GPC_PGC_ACK_SEL_A7 0x24
32 #define GPC_IMR1_CORE0 0x30
33 #define GPC_IMR1_CORE1 0x40
34 #define GPC_IMR1_M4 0x50
35 #define GPC_PGC_CPU_MAPPING 0xec
36 #define GPC_PGC_C0_PUPSCR 0x804
37 #define GPC_PGC_SCU_TIMING 0x890
38 #define GPC_PGC_C1_PUPSCR 0x844
39
40 #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
41 #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
42 #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
43 #define BM_SLPCR_EN_DSM 0x80000000
44 #define BM_SLPCR_RBC_EN 0x40000000
45 #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
46 #define BM_SLPCR_VSTBY 0x4
47 #define BM_SLPCR_SBYOS 0x2
48 #define BM_SLPCR_BYPASS_PMIC_READY 0x1
49 #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
50
51 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
52 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
53
54 #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
55
56 #if defined(CONFIG_IMX_THERMAL)
57 static const struct imx_thermal_plat imx7_thermal_plat = {
58 .regs = (void *)ANATOP_BASE_ADDR,
59 .fuse_bank = 3,
60 .fuse_word = 3,
61 };
62
63 U_BOOT_DRVINFO(imx7_thermal) = {
64 .name = "imx_thermal",
65 .plat = &imx7_thermal_plat,
66 };
67 #endif
68
69 #if CONFIG_IS_ENABLED(IMX_RDC)
70 /*
71 * In current design, if any peripheral was assigned to both A7 and M4,
72 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
73 * low power mode. So M4 sleep will cause some peripherals fail to work
74 * at A7 core side. At default, all resources are in domain 0 - 3.
75 *
76 * There are 26 peripherals impacted by this IC issue:
77 * SIM2(sim2/emvsim2)
78 * SIM1(sim1/emvsim1)
79 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
80 * SAI1/SAI2/SAI3
81 * WDOG1/WDOG2/WDOG3/WDOG4
82 * GPT1/GPT2/GPT3/GPT4
83 * PWM1/PWM2/PWM3/PWM4
84 * ENET1/ENET2
85 * Software Workaround:
86 * Here we setup some resources to domain 0 where M4 codes will move
87 * the M4 out of this domain. Then M4 is not able to access them any longer.
88 * This is a workaround for ic issue. So the peripherals are not shared
89 * by them. This way requires the uboot implemented the RDC driver and
90 * set the 26 IPs above to domain 0 only. M4 code will assign resource
91 * to its own domain, if it want to use the resource.
92 */
93 static rdc_peri_cfg_t const resources[] = {
94 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
95 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
96 (RDC_PER_UART1 | RDC_DOMAIN(0)),
97 (RDC_PER_UART2 | RDC_DOMAIN(0)),
98 (RDC_PER_UART3 | RDC_DOMAIN(0)),
99 (RDC_PER_UART4 | RDC_DOMAIN(0)),
100 (RDC_PER_UART5 | RDC_DOMAIN(0)),
101 (RDC_PER_UART6 | RDC_DOMAIN(0)),
102 (RDC_PER_UART7 | RDC_DOMAIN(0)),
103 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
104 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
105 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
106 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
107 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
108 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
109 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
110 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
111 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
112 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
113 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
114 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
115 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
116 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
117 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
118 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
119 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
120 };
121
isolate_resource(void)122 static void isolate_resource(void)
123 {
124 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
125 }
126 #endif
127
128 #if defined(CONFIG_IMX_HAB)
129 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
130 .bank = 1,
131 .word = 3,
132 };
133 #endif
134
is_mx7d(void)135 static bool is_mx7d(void)
136 {
137 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
138 struct fuse_bank *bank = &ocotp->bank[1];
139 struct fuse_bank1_regs *fuse =
140 (struct fuse_bank1_regs *)bank->fuse_regs;
141 int val;
142
143 val = readl(&fuse->tester4);
144 if (val & 1)
145 return false;
146 else
147 return true;
148 }
149
get_cpu_rev(void)150 u32 get_cpu_rev(void)
151 {
152 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
153 ANATOP_BASE_ADDR;
154 u32 reg = readl(&ccm_anatop->digprog);
155 u32 type = (reg >> 16) & 0xff;
156
157 if (!is_mx7d())
158 type = MXC_CPU_MX7S;
159
160 reg &= 0xff;
161 return (type << 12) | reg;
162 }
163
164 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)165 u32 __weak get_board_rev(void)
166 {
167 return get_cpu_rev();
168 }
169 #endif
170
imx_enet_mdio_fixup(void)171 static void imx_enet_mdio_fixup(void)
172 {
173 struct iomuxc_gpr_base_regs *gpr_regs =
174 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
175
176 /*
177 * The management data input/output (MDIO) requires open-drain,
178 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
179 * this feature. So to TO1.1, need to enable open drain by setting
180 * bits GPR0[8:7].
181 */
182
183 if (soc_rev() >= CHIP_REV_1_1) {
184 setbits_le32(&gpr_regs->gpr[0],
185 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
186 }
187 }
188
init_cpu_basic(void)189 static void init_cpu_basic(void)
190 {
191 imx_enet_mdio_fixup();
192
193 #ifdef CONFIG_APBH_DMA
194 /* Start APBH DMA */
195 mxs_dma_init();
196 #endif
197 }
198
199 #ifdef CONFIG_IMX_BOOTAUX
200 /*
201 * Table of mappings of physical mem regions in both
202 * Cortex-A7 and Cortex-M4 address spaces.
203 *
204 * For additional details check sections 2.1.2 and 2.1.3 in
205 * i.MX7Dual Applications Processor Reference Manual
206 *
207 */
208 const struct rproc_att hostmap[] = {
209 /* aux core , host core, size */
210 { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
211 { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
212 { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
213 { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
214 { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
215 { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
216 { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
217 { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
218 { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
219 { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
220 { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
221 { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
222 { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
223 { /* sentinel */ }
224 };
225 #endif
226
227 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
228 /* enable all periherial can be accessed in nosec mode */
init_csu(void)229 static void init_csu(void)
230 {
231 int i = 0;
232
233 for (i = 0; i < CSU_NUM_REGS; i++)
234 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
235 }
236
imx_gpcv2_init(void)237 static void imx_gpcv2_init(void)
238 {
239 u32 val, i;
240
241 /*
242 * Force IOMUXC irq pending, so that the interrupt to GPC can be
243 * used to deassert dsm_request signal when the signal gets
244 * asserted unexpectedly.
245 */
246 val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
247 val |= BM_IOMUXC_GPR1_IRQ;
248 writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
249
250 /* Initially mask all interrupts */
251 for (i = 0; i < 4; i++) {
252 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
253 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
254 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
255 }
256
257 /* set SCU timing */
258 writel((0x59 << 10) | 0x5B | (0x2 << 20),
259 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
260
261 /* only external IRQs to wake up LPM and core 0/1 */
262 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
263 val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
264 writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
265
266 /* set C0 power up timming per design requirement */
267 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
268 val &= ~BM_GPC_PGC_CORE_PUPSCR;
269 val |= (0x1A << 7);
270 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
271
272 /* set C1 power up timming per design requirement */
273 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
274 val &= ~BM_GPC_PGC_CORE_PUPSCR;
275 val |= (0x1A << 7);
276 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
277
278 /* dummy ack for time slot by default */
279 writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
280 BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
281 GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
282
283 /* mask M4 DSM trigger */
284 writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
285 BM_LPCR_M4_MASK_DSM_TRIGGER,
286 GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
287
288 /* set mega/fast mix in A7 domain */
289 writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
290
291 /* DSM related settings */
292 val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
293 val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
294 BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
295 BM_SLPCR_REG_BYPASS_COUNT);
296 val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
297 writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
298
299 /*
300 * disabling RBC need to delay at least 2 cycles of CKIL(32K)
301 * due to hardware design requirement, which is
302 * ~61us, here we use 65us for safe
303 */
304 udelay(65);
305 }
306
arch_cpu_init(void)307 int arch_cpu_init(void)
308 {
309 init_aips();
310
311 init_csu();
312 /* Disable PDE bit of WMCR register */
313 imx_wdog_disable_powerdown();
314
315 init_cpu_basic();
316
317 #if CONFIG_IS_ENABLED(IMX_RDC)
318 isolate_resource();
319 #endif
320
321 init_snvs();
322
323 imx_gpcv2_init();
324
325 return 0;
326 }
327 #else
arch_cpu_init(void)328 int arch_cpu_init(void)
329 {
330 init_cpu_basic();
331
332 return 0;
333 }
334 #endif
335
336 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)337 int arch_misc_init(void)
338 {
339 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
340 if (is_mx7d())
341 env_set("soc", "imx7d");
342 else
343 env_set("soc", "imx7s");
344 #endif
345
346 #ifdef CONFIG_FSL_CAAM
347 sec_init();
348 #endif
349
350 return 0;
351 }
352 #endif
353
354 #ifdef CONFIG_SERIAL_TAG
355 /*
356 * OCOTP_TESTER
357 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
358 * OCOTP_TESTER describes a unique ID based on silicon wafer
359 * and die X/Y position
360 *
361 * OCOTOP_TESTER offset 0x410
362 * 31:0 fuse 0
363 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
364 *
365 * OCOTP_TESTER1 offset 0x420
366 * 31:24 fuse 1
367 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
368 * 23:16 fuse 1
369 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
370 * 15:11 fuse 1
371 * The wafer number of the wafer on which the device was fabricated/SJC
372 * CHALLENGE/ Unique ID
373 * 10:0 fuse 1
374 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
375 */
get_board_serial(struct tag_serialnr * serialnr)376 void get_board_serial(struct tag_serialnr *serialnr)
377 {
378 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
379 struct fuse_bank *bank = &ocotp->bank[0];
380 struct fuse_bank0_regs *fuse =
381 (struct fuse_bank0_regs *)bank->fuse_regs;
382
383 serialnr->low = fuse->tester0;
384 serialnr->high = fuse->tester1;
385 }
386 #endif
387
set_wdog_reset(struct wdog_regs * wdog)388 void set_wdog_reset(struct wdog_regs *wdog)
389 {
390 u32 reg = readw(&wdog->wcr);
391 /*
392 * Output WDOG_B signal to reset external pmic or POR_B decided by
393 * the board desgin. Without external reset, the peripherals/DDR/
394 * PMIC are not reset, that may cause system working abnormal.
395 */
396 reg = readw(&wdog->wcr);
397 reg |= 1 << 3;
398 /*
399 * WDZST bit is write-once only bit. Align this bit in kernel,
400 * otherwise kernel code will have no chance to set this bit.
401 */
402 reg |= 1 << 0;
403 writew(reg, &wdog->wcr);
404 }
405
s_init(void)406 void s_init(void)
407 {
408 /* clock configuration. */
409 clock_init();
410
411 return;
412 }
413
414 #ifndef CONFIG_SPL_BUILD
415 const struct boot_mode soc_boot_modes[] = {
416 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
417 {"primary", MAKE_CFGVAL_PRIMARY_BOOT},
418 {"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
419 {NULL, 0},
420 };
421
boot_mode_getprisec(void)422 int boot_mode_getprisec(void)
423 {
424 struct src *psrc = (struct src *)SRC_BASE_ADDR;
425
426 return !!(readl(&psrc->gpr10) & IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT);
427 }
428 #endif
429
reset_misc(void)430 void reset_misc(void)
431 {
432 #ifndef CONFIG_SPL_BUILD
433 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
434 lcdif_power_down();
435 #endif
436 #endif
437 }
438
439