1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * K3: AM6 SoC definitions, structures etc. 4 * 5 * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 #ifndef __ASM_ARCH_AM6_HARDWARE_H 8 #define __ASM_ARCH_AM6_HARDWARE_H 9 10 #include <config.h> 11 #ifndef __ASSEMBLY__ 12 #include <linux/bitops.h> 13 #endif 14 15 #define CTRL_MMR0_BASE 0x00100000 16 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) 17 18 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0) 19 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0 20 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4) 21 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 4 22 #define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK GENMASK(12, 12) 23 #define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT 12 24 #define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK GENMASK(14, 14) 25 #define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14 26 #define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK GENMASK(17, 17) 27 #define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12 28 #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT 9 29 #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9) 30 31 #define WKUP_CTRL_MMR0_BASE 0x43000000 32 #define MCU_CTRL_MMR0_BASE 0x40f00000 33 34 /* 35 * The CTRL_MMR0 memory space is divided into several equally-spaced 36 * partitions, so defining the partition size allows us to determine 37 * register addresses common to those partitions. 38 */ 39 #define CTRL_MMR0_PARTITION_SIZE 0x4000 40 41 /* 42 * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism 43 * shared register definitions. 44 */ 45 #define CTRLMMR_LOCK_KICK0 0x01008 46 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 47 #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) 48 #define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 49 #define CTRLMMR_LOCK_KICK1 0x0100c 50 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a 51 52 /* MCU SCRATCHPAD usage */ 53 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE 54 55 #endif /* __ASM_ARCH_AM6_HARDWARE_H */ 56