1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * K3: J721E SoC definitions, structures etc. 4 * 5 * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 #ifndef __ASM_ARCH_J721E_HARDWARE_H 8 #define __ASM_ARCH_J721E_HARDWARE_H 9 10 #include <config.h> 11 #ifndef __ASSEMBLY__ 12 #include <linux/bitops.h> 13 #endif 14 15 #define CTRL_MMR0_BASE 0x00100000 16 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) 17 18 #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) 19 #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 20 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) 21 #define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1 22 #define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6) 23 #define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6 24 #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) 25 #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 26 27 #define WKUP_CTRL_MMR0_BASE 0x43000000 28 #define MCU_CTRL_MMR0_BASE 0x40f00000 29 30 #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) 31 #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) 32 #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 33 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) 34 #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 35 36 /* 37 * The CTRL_MMR0 memory space is divided into several equally-spaced 38 * partitions, so defining the partition size allows us to determine 39 * register addresses common to those partitions. 40 */ 41 #define CTRL_MMR0_PARTITION_SIZE 0x4000 42 43 /* 44 * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism 45 * shared register definitions. 46 */ 47 #define CTRLMMR_LOCK_KICK0 0x01008 48 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 49 #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) 50 #define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 51 #define CTRLMMR_LOCK_KICK1 0x0100c 52 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a 53 54 /* ROM HANDOFF Structure location */ 55 #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cffb00 56 57 /* MCU SCRATCHPAD usage */ 58 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE 59 60 #endif /* __ASM_ARCH_J721E_HARDWARE_H */ 61