1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 */
6
7 #include <clk.h>
8 #include <common.h>
9 #include <dm.h>
10 #include <fdtdec.h>
11 #include <init.h>
12 #include <log.h>
13 #include <ram.h>
14 #include <asm/arch/misc.h>
15 #include <asm/global_data.h>
16 #include <asm/sections.h>
17 #include <dm/uclass.h>
18 #include <linux/bitops.h>
19 #include <linux/io.h>
20
21 #include <dt-bindings/clock/mt7629-clk.h>
22
23 #define L2_CFG_BASE 0x10200000
24 #define L2_CFG_SIZE 0x1000
25 #define L2_SHARE_CFG_MP0 0x7f0
26 #define L2_SHARE_MODE_OFF BIT(8)
27
28 DECLARE_GLOBAL_DATA_PTR;
29
mtk_pll_early_init(void)30 int mtk_pll_early_init(void)
31 {
32 unsigned long pll_rates[] = {
33 [CLK_APMIXED_ARMPLL] = 1250000000,
34 [CLK_APMIXED_MAINPLL] = 1120000000,
35 [CLK_APMIXED_UNIV2PLL] = 1200000000,
36 [CLK_APMIXED_ETH1PLL] = 500000000,
37 [CLK_APMIXED_ETH2PLL] = 700000000,
38 [CLK_APMIXED_SGMIPLL] = 650000000,
39 };
40 struct udevice *dev;
41 int ret, i;
42
43 ret = uclass_get_device_by_driver(UCLASS_CLK,
44 DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
45 if (ret)
46 return ret;
47
48 /* configure default rate then enable apmixedsys */
49 for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
50 struct clk clk = { .id = i, .dev = dev };
51
52 ret = clk_set_rate(&clk, pll_rates[i]);
53 if (ret)
54 return ret;
55
56 ret = clk_enable(&clk);
57 if (ret)
58 return ret;
59 }
60
61 /* setup mcu bus */
62 ret = uclass_get_device_by_driver(UCLASS_SYSCON,
63 DM_DRIVER_GET(mtk_mcucfg), &dev);
64 if (ret)
65 return ret;
66
67 return 0;
68 }
69
mtk_soc_early_init(void)70 int mtk_soc_early_init(void)
71 {
72 struct udevice *dev;
73 int ret;
74
75 /* initialize early clocks */
76 ret = mtk_pll_early_init();
77 if (ret)
78 return ret;
79
80 ret = uclass_first_device_err(UCLASS_RAM, &dev);
81 if (ret)
82 return ret;
83
84 return 0;
85 }
86
mach_cpu_init(void)87 int mach_cpu_init(void)
88 {
89 void __iomem *base;
90
91 base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
92
93 /* disable L2C shared mode */
94 writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
95
96 return 0;
97 }
98
dram_init(void)99 int dram_init(void)
100 {
101 struct ram_info ram;
102 struct udevice *dev;
103 int ret;
104
105 ret = uclass_first_device_err(UCLASS_RAM, &dev);
106 if (ret)
107 return ret;
108
109 ret = ram_get_info(dev, &ram);
110 if (ret)
111 return ret;
112
113 debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
114
115 gd->ram_size = ram.size;
116
117 return 0;
118 }
119
print_cpuinfo(void)120 int print_cpuinfo(void)
121 {
122 void __iomem *chipid;
123 u32 hwcode, swver;
124
125 chipid = ioremap(VER_BASE, VER_SIZE);
126 hwcode = readl(chipid + APHW_CODE);
127 swver = readl(chipid + APSW_VER);
128
129 printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
130
131 return 0;
132 }
133