1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Configuration for MediaTek MT8518 SoC
4 *
5 * Copyright (C) 2019 MediaTek Inc.
6 * Author: Mingming Lee <mingming.lee@mediatek.com>
7 */
8
9 #include <clk.h>
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <fdtdec.h>
14 #include <init.h>
15 #include <ram.h>
16 #include <asm/arch/misc.h>
17 #include <asm/armv8/mmu.h>
18 #include <asm/cache.h>
19 #include <asm/global_data.h>
20 #include <asm/sections.h>
21 #include <dm/uclass.h>
22 #include <dt-bindings/clock/mt8518-clk.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
dram_init(void)26 int dram_init(void)
27 {
28 int ret;
29
30 ret = fdtdec_setup_memory_banksize();
31 if (ret)
32 return ret;
33
34 return fdtdec_setup_mem_size_base();
35 }
36
dram_init_banksize(void)37 int dram_init_banksize(void)
38 {
39 gd->bd->bi_dram[0].start = gd->ram_base;
40 gd->bd->bi_dram[0].size = gd->ram_size;
41
42 return 0;
43 }
44
reset_cpu(ulong addr)45 void reset_cpu(ulong addr)
46 {
47 psci_system_reset();
48 }
49
print_cpuinfo(void)50 int print_cpuinfo(void)
51 {
52 printf("CPU: MediaTek MT8518\n");
53 return 0;
54 }
55
56 static struct mm_region mt8518_mem_map[] = {
57 {
58 /* DDR */
59 .virt = 0x40000000UL,
60 .phys = 0x40000000UL,
61 .size = 0x20000000UL,
62 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
63 }, {
64 .virt = 0x00000000UL,
65 .phys = 0x00000000UL,
66 .size = 0x20000000UL,
67 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
68 PTE_BLOCK_NON_SHARE |
69 PTE_BLOCK_PXN | PTE_BLOCK_UXN
70 }, {
71 0,
72 }
73 };
74
75 struct mm_region *mem_map = mt8518_mem_map;
76