1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <net.h>
10 #include <asm/arch/boot.h>
11 #include <asm/arch/eth.h>
12 #include <asm/arch/axg.h>
13 #include <asm/arch/mem.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/armv8/mmu.h>
17 #include <linux/sizes.h>
18 #include <usb.h>
19 #include <linux/usb/otg.h>
20 #include <asm/arch/usb-gx.h>
21 #include <usb/dwc2_udc.h>
22 #include <clk.h>
23 #include <phy.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
meson_get_boot_device(void)27 int meson_get_boot_device(void)
28 {
29 return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
30 }
31
32 /* Configure the reserved memory zones exported by the secure registers
33 * into EFI and DTB reserved memory entries.
34 */
meson_init_reserved_memory(void * fdt)35 void meson_init_reserved_memory(void *fdt)
36 {
37 u64 bl31_size, bl31_start;
38 u64 bl32_size, bl32_start;
39 u32 reg;
40
41 /*
42 * Get ARM Trusted Firmware reserved memory zones in :
43 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
44 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
45 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
46 */
47 reg = readl(AXG_AO_SEC_GP_CFG3);
48
49 bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
50 >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
51 bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
52
53 bl31_start = readl(AXG_AO_SEC_GP_CFG5);
54 bl32_start = readl(AXG_AO_SEC_GP_CFG4);
55
56 /* Add BL31 reserved zone */
57 if (bl31_start && bl31_size)
58 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
59
60 /* Add BL32 reserved zone */
61 if (bl32_start && bl32_size)
62 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
63 }
64
get_effective_memsize(void)65 phys_size_t get_effective_memsize(void)
66 {
67 /* Size is reported in MiB, convert it in bytes */
68 return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
69 >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
70 }
71
72 static struct mm_region axg_mem_map[] = {
73 {
74 .virt = 0x0UL,
75 .phys = 0x0UL,
76 .size = 0x80000000UL,
77 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
78 PTE_BLOCK_INNER_SHARE
79 }, {
80 .virt = 0xf0000000UL,
81 .phys = 0xf0000000UL,
82 .size = 0x10000000UL,
83 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
84 PTE_BLOCK_NON_SHARE |
85 PTE_BLOCK_PXN | PTE_BLOCK_UXN
86 }, {
87 /* List terminator */
88 0,
89 }
90 };
91
92 struct mm_region *mem_map = axg_mem_map;
93
94 /* Configure the Ethernet MAC with the requested interface mode
95 * with some optional flags.
96 */
meson_eth_init(phy_interface_t mode,unsigned int flags)97 void meson_eth_init(phy_interface_t mode, unsigned int flags)
98 {
99 switch (mode) {
100 case PHY_INTERFACE_MODE_RGMII:
101 case PHY_INTERFACE_MODE_RGMII_ID:
102 case PHY_INTERFACE_MODE_RGMII_RXID:
103 case PHY_INTERFACE_MODE_RGMII_TXID:
104 /* Set RGMII mode */
105 setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
106 AXG_ETH_REG_0_TX_PHASE(1) |
107 AXG_ETH_REG_0_TX_RATIO(4) |
108 AXG_ETH_REG_0_PHY_CLK_EN |
109 AXG_ETH_REG_0_CLK_EN);
110 break;
111
112 case PHY_INTERFACE_MODE_RMII:
113 /* Set RMII mode */
114 out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
115 AXG_ETH_REG_0_INVERT_RMII_CLK |
116 AXG_ETH_REG_0_CLK_EN);
117 break;
118
119 default:
120 printf("Invalid Ethernet interface mode\n");
121 return;
122 }
123
124 /* Enable power gate */
125 clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
126 }
127
128 #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
129 CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
130 static struct dwc2_plat_otg_data meson_gx_dwc2_data;
131
board_usb_init(int index,enum usb_init_type init)132 int board_usb_init(int index, enum usb_init_type init)
133 {
134 struct fdtdec_phandle_args args;
135 const void *blob = gd->fdt_blob;
136 int node, dwc2_node;
137 struct udevice *dev, *clk_dev;
138 struct clk clk;
139 int ret;
140
141 /* find the usb glue node */
142 node = fdt_node_offset_by_compatible(blob, -1,
143 "amlogic,meson-gxl-usb-ctrl");
144 if (node < 0) {
145 debug("Not found usb-control node\n");
146 return -ENODEV;
147 }
148
149 if (!fdtdec_get_is_enabled(blob, node)) {
150 debug("usb is disabled in the device tree\n");
151 return -ENODEV;
152 }
153
154 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
155 if (ret) {
156 debug("Not found usb-control device\n");
157 return ret;
158 }
159
160 /* find the dwc2 node */
161 dwc2_node = fdt_node_offset_by_compatible(blob, node,
162 "amlogic,meson-g12a-usb");
163 if (dwc2_node < 0) {
164 debug("Not found dwc2 node\n");
165 return -ENODEV;
166 }
167
168 if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
169 debug("dwc2 is disabled in the device tree\n");
170 return -ENODEV;
171 }
172
173 meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
174 if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
175 debug("usbotg: can't get base address\n");
176 return -ENODATA;
177 }
178
179 /* Enable clock */
180 ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
181 "#clock-cells", 0, 0, &args);
182 if (ret) {
183 debug("usbotg has no clocks defined in the device tree\n");
184 return ret;
185 }
186
187 ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
188 if (ret)
189 return ret;
190
191 if (args.args_count != 1) {
192 debug("Can't find clock ID in the device tree\n");
193 return -ENODATA;
194 }
195
196 clk.dev = clk_dev;
197 clk.id = args.args[0];
198
199 ret = clk_enable(&clk);
200 if (ret) {
201 debug("Failed to enable usbotg clock\n");
202 return ret;
203 }
204
205 meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
206 "g-rx-fifo-size", 0);
207 meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
208 "g-np-tx-fifo-size", 0);
209 meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
210 "g-tx-fifo-size", 0);
211
212 /* Switch to peripheral mode */
213 ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
214 if (ret)
215 return ret;
216
217 return dwc2_udc_probe(&meson_gx_dwc2_data);
218 }
219
board_usb_cleanup(int index,enum usb_init_type init)220 int board_usb_cleanup(int index, enum usb_init_type init)
221 {
222 const void *blob = gd->fdt_blob;
223 struct udevice *dev;
224 int node;
225 int ret;
226
227 /* find the usb glue node */
228 node = fdt_node_offset_by_compatible(blob, -1,
229 "amlogic,meson-gxl-usb-ctrl");
230 if (node < 0) {
231 debug("Not found usb-control node\n");
232 return -ENODEV;
233 }
234
235 if (!fdtdec_get_is_enabled(blob, node))
236 return -ENODEV;
237
238 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
239 if (ret)
240 return ret;
241
242 /* Switch to OTG mode */
243 ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
244 if (ret)
245 return ret;
246
247 return 0;
248 }
249 #endif
250