1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <log.h>
10 #include <net.h>
11 #include <asm/arch/boot.h>
12 #include <asm/arch/eth.h>
13 #include <asm/arch/g12a.h>
14 #include <asm/arch/mem.h>
15 #include <asm/arch/meson-vpu.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/armv8/mmu.h>
19 #include <linux/sizes.h>
20 #include <usb.h>
21 #include <linux/usb/otg.h>
22 #include <asm/arch/usb.h>
23 #include <usb/dwc2_udc.h>
24 #include <phy.h>
25 #include <clk.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
meson_get_boot_device(void)29 int meson_get_boot_device(void)
30 {
31 return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
32 }
33
34 /* Configure the reserved memory zones exported by the secure registers
35 * into EFI and DTB reserved memory entries.
36 */
meson_init_reserved_memory(void * fdt)37 void meson_init_reserved_memory(void *fdt)
38 {
39 u64 bl31_size, bl31_start;
40 u64 bl32_size, bl32_start;
41 u32 reg;
42
43 /*
44 * Get ARM Trusted Firmware reserved memory zones in :
45 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
46 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
47 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
48 */
49 reg = readl(G12A_AO_SEC_GP_CFG3);
50
51 bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
52 >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
53 bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
54
55 bl31_start = readl(G12A_AO_SEC_GP_CFG5);
56 bl32_start = readl(G12A_AO_SEC_GP_CFG4);
57
58 /* Add BL31 reserved zone */
59 if (bl31_start && bl31_size)
60 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
61
62 /* Add BL32 reserved zone */
63 if (bl32_start && bl32_size)
64 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
65
66 #if defined(CONFIG_VIDEO_MESON)
67 meson_vpu_rsv_fb(fdt);
68 #endif
69 }
70
get_effective_memsize(void)71 phys_size_t get_effective_memsize(void)
72 {
73 /* Size is reported in MiB, convert it in bytes */
74 return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
75 >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
76 }
77
78 static struct mm_region g12a_mem_map[] = {
79 {
80 .virt = 0x0UL,
81 .phys = 0x0UL,
82 .size = 0xf5000000UL,
83 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
84 PTE_BLOCK_INNER_SHARE
85 }, {
86 .virt = 0xf5000000UL,
87 .phys = 0xf5000000UL,
88 .size = 0x0b000000UL,
89 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
90 PTE_BLOCK_NON_SHARE |
91 PTE_BLOCK_PXN | PTE_BLOCK_UXN
92 }, {
93 /* List terminator */
94 0,
95 }
96 };
97
98 struct mm_region *mem_map = g12a_mem_map;
99
g12a_enable_external_mdio(void)100 static void g12a_enable_external_mdio(void)
101 {
102 writel(0x0, ETH_PHY_CNTL2);
103 }
104
g12a_enable_internal_mdio(void)105 static void g12a_enable_internal_mdio(void)
106 {
107 /* Fire up the PHY PLL */
108 writel(0x29c0040a, ETH_PLL_CNTL0);
109 writel(0x927e0000, ETH_PLL_CNTL1);
110 writel(0xac5f49e5, ETH_PLL_CNTL2);
111 writel(0x00000000, ETH_PLL_CNTL3);
112 writel(0x00000000, ETH_PLL_CNTL4);
113 writel(0x20200000, ETH_PLL_CNTL5);
114 writel(0x0000c002, ETH_PLL_CNTL6);
115 writel(0x00000023, ETH_PLL_CNTL7);
116 writel(0x39c0040a, ETH_PLL_CNTL0);
117 writel(0x19c0040a, ETH_PLL_CNTL0);
118
119 /* Select the internal MDIO */
120 writel(0x33000180, ETH_PHY_CNTL0);
121 writel(0x00074043, ETH_PHY_CNTL1);
122 writel(0x00000260, ETH_PHY_CNTL2);
123 }
124
125 /* Configure the Ethernet MAC with the requested interface mode
126 * with some optional flags.
127 */
meson_eth_init(phy_interface_t mode,unsigned int flags)128 void meson_eth_init(phy_interface_t mode, unsigned int flags)
129 {
130 switch (mode) {
131 case PHY_INTERFACE_MODE_RGMII:
132 case PHY_INTERFACE_MODE_RGMII_ID:
133 case PHY_INTERFACE_MODE_RGMII_RXID:
134 case PHY_INTERFACE_MODE_RGMII_TXID:
135 /* Set RGMII mode */
136 setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
137 G12A_ETH_REG_0_TX_PHASE(1) |
138 G12A_ETH_REG_0_TX_RATIO(4) |
139 G12A_ETH_REG_0_PHY_CLK_EN |
140 G12A_ETH_REG_0_CLK_EN);
141 g12a_enable_external_mdio();
142 break;
143
144 case PHY_INTERFACE_MODE_RMII:
145 /* Set RMII mode */
146 out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
147 G12A_ETH_REG_0_INVERT_RMII_CLK |
148 G12A_ETH_REG_0_CLK_EN);
149
150 /* Use G12A RMII Internal PHY */
151 if (flags & MESON_USE_INTERNAL_RMII_PHY)
152 g12a_enable_internal_mdio();
153 else
154 g12a_enable_external_mdio();
155
156 break;
157
158 default:
159 printf("Invalid Ethernet interface mode\n");
160 return;
161 }
162
163 /* Enable power gate */
164 clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
165 }
166
167 #if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
168 CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
169 static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
170
board_usb_init(int index,enum usb_init_type init)171 int board_usb_init(int index, enum usb_init_type init)
172 {
173 struct fdtdec_phandle_args args;
174 const void *blob = gd->fdt_blob;
175 int node, dwc2_node;
176 struct udevice *dev, *clk_dev;
177 struct clk clk;
178 int ret;
179
180 /* find the usb glue node */
181 node = fdt_node_offset_by_compatible(blob, -1,
182 "amlogic,meson-g12a-usb-ctrl");
183 if (node < 0) {
184 debug("Not found usb-control node\n");
185 return -ENODEV;
186 }
187
188 if (!fdtdec_get_is_enabled(blob, node)) {
189 debug("usb is disabled in the device tree\n");
190 return -ENODEV;
191 }
192
193 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
194 if (ret) {
195 debug("Not found usb-control device\n");
196 return ret;
197 }
198
199 /* find the dwc2 node */
200 dwc2_node = fdt_node_offset_by_compatible(blob, node,
201 "amlogic,meson-g12a-usb");
202 if (dwc2_node < 0) {
203 debug("Not found dwc2 node\n");
204 return -ENODEV;
205 }
206
207 if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
208 debug("dwc2 is disabled in the device tree\n");
209 return -ENODEV;
210 }
211
212 meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
213 if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
214 debug("usbotg: can't get base address\n");
215 return -ENODATA;
216 }
217
218 /* Enable clock */
219 ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
220 "#clock-cells", 0, 0, &args);
221 if (ret) {
222 debug("usbotg has no clocks defined in the device tree\n");
223 return ret;
224 }
225
226 ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
227 if (ret)
228 return ret;
229
230 if (args.args_count != 1) {
231 debug("Can't find clock ID in the device tree\n");
232 return -ENODATA;
233 }
234
235 clk.dev = clk_dev;
236 clk.id = args.args[0];
237
238 ret = clk_enable(&clk);
239 if (ret) {
240 debug("Failed to enable usbotg clock\n");
241 return ret;
242 }
243
244 meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
245 "g-rx-fifo-size", 0);
246 meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
247 "g-np-tx-fifo-size", 0);
248 meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
249 "g-tx-fifo-size", 0);
250
251 /* Switch to peripheral mode */
252 ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
253 if (ret)
254 return ret;
255
256 return dwc2_udc_probe(&meson_g12a_dwc2_data);
257 }
258
board_usb_cleanup(int index,enum usb_init_type init)259 int board_usb_cleanup(int index, enum usb_init_type init)
260 {
261 const void *blob = gd->fdt_blob;
262 struct udevice *dev;
263 int node;
264 int ret;
265
266 /* find the usb glue node */
267 node = fdt_node_offset_by_compatible(blob, -1,
268 "amlogic,meson-g12a-usb-ctrl");
269 if (node < 0)
270 return -ENODEV;
271
272 if (!fdtdec_get_is_enabled(blob, node))
273 return -ENODEV;
274
275 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
276 if (ret)
277 return ret;
278
279 /* Switch to OTG mode */
280 ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
281 if (ret)
282 return ret;
283
284 return 0;
285 }
286 #endif
287