1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <net.h>
10 #include <asm/arch/boot.h>
11 #include <asm/arch/eth.h>
12 #include <asm/arch/gx.h>
13 #include <asm/arch/mem.h>
14 #include <asm/arch/meson-vpu.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <asm/armv8/mmu.h>
18 #include <linux/sizes.h>
19 #include <usb.h>
20 #include <linux/usb/otg.h>
21 #include <asm/arch/usb-gx.h>
22 #include <usb/dwc2_udc.h>
23 #include <clk.h>
24 #include <phy.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
meson_get_boot_device(void)28 int meson_get_boot_device(void)
29 {
30 return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
31 }
32
33 /* Configure the reserved memory zones exported by the secure registers
34 * into EFI and DTB reserved memory entries.
35 */
meson_init_reserved_memory(void * fdt)36 void meson_init_reserved_memory(void *fdt)
37 {
38 u64 bl31_size, bl31_start;
39 u64 bl32_size, bl32_start;
40 u32 reg;
41
42 /*
43 * Get ARM Trusted Firmware reserved memory zones in :
44 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
45 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
46 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
47 */
48 reg = readl(GX_AO_SEC_GP_CFG3);
49
50 bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
51 >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
52 bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
53
54 bl31_start = readl(GX_AO_SEC_GP_CFG5);
55 bl32_start = readl(GX_AO_SEC_GP_CFG4);
56
57 /*
58 * Early Meson GX Firmware revisions did not provide the reserved
59 * memory zones in the registers, keep fixed memory zone handling.
60 */
61 if (IS_ENABLED(CONFIG_MESON_GX) &&
62 !reg && !bl31_start && !bl32_start) {
63 bl31_start = 0x10000000;
64 bl31_size = 0x200000;
65 }
66
67 /* Add first 16MiB reserved zone */
68 meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
69
70 /* Add BL31 reserved zone */
71 if (bl31_start && bl31_size)
72 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
73
74 /* Add BL32 reserved zone */
75 if (bl32_start && bl32_size)
76 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
77
78 #if defined(CONFIG_VIDEO_MESON)
79 meson_vpu_rsv_fb(fdt);
80 #endif
81 }
82
get_effective_memsize(void)83 phys_size_t get_effective_memsize(void)
84 {
85 /* Size is reported in MiB, convert it in bytes */
86 return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
87 >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
88 }
89
90 static struct mm_region gx_mem_map[] = {
91 {
92 .virt = 0x0UL,
93 .phys = 0x0UL,
94 .size = 0xc0000000UL,
95 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
96 PTE_BLOCK_INNER_SHARE
97 }, {
98 .virt = 0xc0000000UL,
99 .phys = 0xc0000000UL,
100 .size = 0x30000000UL,
101 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
102 PTE_BLOCK_NON_SHARE |
103 PTE_BLOCK_PXN | PTE_BLOCK_UXN
104 }, {
105 /* List terminator */
106 0,
107 }
108 };
109
110 struct mm_region *mem_map = gx_mem_map;
111
112 /* Configure the Ethernet MAC with the requested interface mode
113 * with some optional flags.
114 */
meson_eth_init(phy_interface_t mode,unsigned int flags)115 void meson_eth_init(phy_interface_t mode, unsigned int flags)
116 {
117 switch (mode) {
118 case PHY_INTERFACE_MODE_RGMII:
119 case PHY_INTERFACE_MODE_RGMII_ID:
120 case PHY_INTERFACE_MODE_RGMII_RXID:
121 case PHY_INTERFACE_MODE_RGMII_TXID:
122 /* Set RGMII mode */
123 setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
124 GX_ETH_REG_0_TX_PHASE(1) |
125 GX_ETH_REG_0_TX_RATIO(4) |
126 GX_ETH_REG_0_PHY_CLK_EN |
127 GX_ETH_REG_0_CLK_EN);
128
129 /* Reset to external PHY */
130 if(!IS_ENABLED(CONFIG_MESON_GXBB))
131 writel(0x2009087f, GX_ETH_REG_3);
132
133 break;
134
135 case PHY_INTERFACE_MODE_RMII:
136 /* Set RMII mode */
137 out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
138 GX_ETH_REG_0_CLK_EN);
139
140 /* Use GXL RMII Internal PHY (also on GXM) */
141 if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
142 if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
143 writel(0x10110181, GX_ETH_REG_2);
144 writel(0xe40908ff, GX_ETH_REG_3);
145 } else
146 writel(0x2009087f, GX_ETH_REG_3);
147 }
148
149 break;
150
151 default:
152 printf("Invalid Ethernet interface mode\n");
153 return;
154 }
155
156 /* Enable power gate */
157 clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
158 }
159
160 #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
161 CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
162 static struct dwc2_plat_otg_data meson_gx_dwc2_data;
163
board_usb_init(int index,enum usb_init_type init)164 int board_usb_init(int index, enum usb_init_type init)
165 {
166 struct fdtdec_phandle_args args;
167 const void *blob = gd->fdt_blob;
168 int node, dwc2_node;
169 struct udevice *dev, *clk_dev;
170 struct clk clk;
171 int ret;
172
173 /* find the usb glue node */
174 node = fdt_node_offset_by_compatible(blob, -1,
175 "amlogic,meson-gxl-usb-ctrl");
176 if (node < 0) {
177 node = fdt_node_offset_by_compatible(blob, -1,
178 "amlogic,meson-gxm-usb-ctrl");
179 if (node < 0) {
180 debug("Not found usb-control node\n");
181 return -ENODEV;
182 }
183 }
184
185 if (!fdtdec_get_is_enabled(blob, node)) {
186 debug("usb is disabled in the device tree\n");
187 return -ENODEV;
188 }
189
190 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
191 if (ret) {
192 debug("Not found usb-control device\n");
193 return ret;
194 }
195
196 /* find the dwc2 node */
197 dwc2_node = fdt_node_offset_by_compatible(blob, node,
198 "amlogic,meson-g12a-usb");
199 if (dwc2_node < 0) {
200 debug("Not found dwc2 node\n");
201 return -ENODEV;
202 }
203
204 if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
205 debug("dwc2 is disabled in the device tree\n");
206 return -ENODEV;
207 }
208
209 meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
210 if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
211 debug("usbotg: can't get base address\n");
212 return -ENODATA;
213 }
214
215 /* Enable clock */
216 ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
217 "#clock-cells", 0, 0, &args);
218 if (ret) {
219 debug("usbotg has no clocks defined in the device tree\n");
220 return ret;
221 }
222
223 ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
224 if (ret)
225 return ret;
226
227 if (args.args_count != 1) {
228 debug("Can't find clock ID in the device tree\n");
229 return -ENODATA;
230 }
231
232 clk.dev = clk_dev;
233 clk.id = args.args[0];
234
235 ret = clk_enable(&clk);
236 if (ret) {
237 debug("Failed to enable usbotg clock\n");
238 return ret;
239 }
240
241 meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
242 "g-rx-fifo-size", 0);
243 meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
244 "g-np-tx-fifo-size", 0);
245 meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
246 "g-tx-fifo-size", 0);
247
248 /* Switch to peripheral mode */
249 ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
250 if (ret)
251 return ret;
252
253 return dwc2_udc_probe(&meson_gx_dwc2_data);
254 }
255
board_usb_cleanup(int index,enum usb_init_type init)256 int board_usb_cleanup(int index, enum usb_init_type init)
257 {
258 const void *blob = gd->fdt_blob;
259 struct udevice *dev;
260 int node;
261 int ret;
262
263 /* find the usb glue node */
264 node = fdt_node_offset_by_compatible(blob, -1,
265 "amlogic,meson-gxl-usb-ctrl");
266 if (node < 0) {
267 node = fdt_node_offset_by_compatible(blob, -1,
268 "amlogic,meson-gxm-usb-ctrl");
269 if (node < 0) {
270 debug("Not found usb-control node\n");
271 return -ENODEV;
272 }
273 }
274
275 if (!fdtdec_get_is_enabled(blob, node))
276 return -ENODEV;
277
278 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
279 if (ret)
280 return ret;
281
282 /* Switch to OTG mode */
283 ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
284 if (ret)
285 return ret;
286
287 return 0;
288 }
289 #endif
290