1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <linux/libfdt.h>
11 #include <asm/io.h>
12 #include <asm/system.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <asm/armv8/mmu.h>
16
17 /* Armada 7k/8k */
18 #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
19 #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
20 #define RFU_SW_RESET_OFFSET 0
21
22 #define SAR0_REG (MVEBU_REGISTER(0x2400200))
23 #define BOOT_MODE_MASK 0x3f
24 #define BOOT_MODE_OFFSET 4
25
26 /*
27 * The following table includes all memory regions for Armada 7k and
28 * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
29 * define these regions at the beginning of the struct so that they
30 * can be easier removed later dynamically if an Armada 7k device is detected.
31 * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
32 */
33 #define ARMADA_7K8K_COMMON_REGIONS_START 2
34 static struct mm_region mvebu_mem_map[] = {
35 /* Armada 80x0 memory regions include the CP1 (slave) units */
36 {
37 /* SRAM, MMIO regions - CP110 slave region */
38 .phys = 0xf4000000UL,
39 .virt = 0xf4000000UL,
40 .size = 0x02000000UL, /* 32MiB internal registers */
41 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
42 PTE_BLOCK_NON_SHARE
43 },
44 {
45 /* PCI CP1 regions */
46 .phys = 0xfa000000UL,
47 .virt = 0xfa000000UL,
48 .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
49 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
50 PTE_BLOCK_NON_SHARE
51 },
52 /* Armada 80x0 and 70x0 common memory regions start here */
53 {
54 /* RAM */
55 .phys = 0x0UL,
56 .virt = 0x0UL,
57 .size = 0x80000000UL,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
59 PTE_BLOCK_INNER_SHARE
60 },
61 {
62 /* SRAM, MMIO regions - AP806 region */
63 .phys = 0xf0000000UL,
64 .virt = 0xf0000000UL,
65 .size = 0x01000000UL, /* 16MiB internal registers */
66 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
67 PTE_BLOCK_NON_SHARE
68 },
69 {
70 /* SRAM, MMIO regions - CP110 master region */
71 .phys = 0xf2000000UL,
72 .virt = 0xf2000000UL,
73 .size = 0x02000000UL, /* 32MiB internal registers */
74 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
75 PTE_BLOCK_NON_SHARE
76 },
77 {
78 /* PCI CP0 regions */
79 .phys = 0xf6000000UL,
80 .virt = 0xf6000000UL,
81 .size = 0x04000000UL, /* 64MiB CP110 master PCI space */
82 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
83 PTE_BLOCK_NON_SHARE
84 },
85 {
86 0,
87 }
88 };
89
90 struct mm_region *mem_map = mvebu_mem_map;
91
enable_caches(void)92 void enable_caches(void)
93 {
94 /*
95 * Armada 7k is not equipped with the CP110 slave CP. In case this
96 * code runs on an Armada 7k device, lets remove the CP110 slave
97 * entries from the memory mapping by moving the start to the
98 * common regions.
99 */
100 if (of_machine_is_compatible("marvell,armada7040"))
101 mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
102
103 icache_enable();
104 dcache_enable();
105 }
106
reset_cpu(ulong ignored)107 void reset_cpu(ulong ignored)
108 {
109 u32 reg;
110
111 reg = readl(RFU_GLOBAL_SW_RST);
112 reg &= ~(1 << RFU_SW_RESET_OFFSET);
113 writel(reg, RFU_GLOBAL_SW_RST);
114 }
115
116 /*
117 * TODO - implement this functionality using platform
118 * clock driver once it gets available
119 * Return NAND clock in Hz
120 */
mvebu_get_nand_clock(void)121 u32 mvebu_get_nand_clock(void)
122 {
123 unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
124 unsigned long NF_CLOCK_SEL_MASK = 0x1;
125 u32 reg;
126
127 reg = readl(NAND_FLASH_CLK_CTRL);
128 if (reg & NF_CLOCK_SEL_MASK)
129 return 400 * 1000000;
130 else
131 return 250 * 1000000;
132 }
133
mmc_get_env_dev(void)134 int mmc_get_env_dev(void)
135 {
136 u32 reg;
137 unsigned int boot_mode;
138
139 reg = readl(SAR0_REG);
140 boot_mode = (reg >> BOOT_MODE_OFFSET) & BOOT_MODE_MASK;
141
142 switch (boot_mode) {
143 case 0x28:
144 case 0x2a:
145 return 0;
146 case 0x29:
147 case 0x2b:
148 return 1;
149 }
150
151 return CONFIG_SYS_MMC_ENV_DEV;
152 }
153