1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _SYS_ENV_LIB_H 7 #define _SYS_ENV_LIB_H 8 9 #include "../../../drivers/ddr/marvell/a38x/ddr3_init.h" 10 11 /* Serdes definitions */ 12 #define COMMON_PHY_BASE_ADDR 0x18300 13 14 #define DEVICE_CONFIGURATION_REG0 0x18284 15 #define DEVICE_CONFIGURATION_REG1 0x18288 16 #define COMMON_PHY_CONFIGURATION1_REG 0x18300 17 #define COMMON_PHY_CONFIGURATION2_REG 0x18304 18 #define COMMON_PHY_CONFIGURATION4_REG 0x1830c 19 #define COMMON_PHY_STATUS1_REG 0x18318 20 #define COMMON_PHYS_SELECTORS_REG 0x183fc 21 #define SOC_CONTROL_REG1 0x18204 22 #define GENERAL_PURPOSE_RESERVED0_REG 0x182e0 23 #define GBE_CONFIGURATION_REG 0x18460 24 #define DEVICE_SAMPLE_AT_RESET1_REG 0x18600 25 #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604 26 #define DEV_ID_REG 0x18238 27 28 #define CORE_PLL_PARAMETERS_REG 0xe42e0 29 #define CORE_PLL_CONFIG_REG 0xe42e4 30 31 #define QSGMII_CONTROL_REG1 0x18494 32 33 #define DEV_ID_REG_DEVICE_ID_OFFS 16 34 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000 35 36 #define SAR_FREQ_OFFSET 10 37 #define SAR_FREQ_MASK 0x1f 38 #define SAR_DEV_ID_OFFS 27 39 #define SAR_DEV_ID_MASK 0x7 40 41 #define POWER_AND_PLL_CTRL_REG 0xa0004 42 #define CALIBRATION_CTRL_REG 0xa0008 43 #define DFE_REG0 0xa001c 44 #define DFE_REG3 0xa0028 45 #define RESET_DFE_REG 0xa0148 46 #define LOOPBACK_REG 0xa008c 47 #define SYNC_PATTERN_REG 0xa0090 48 #define INTERFACE_REG 0xa0094 49 #define ISOLATE_REG 0xa0098 50 #define MISC_REG 0xa013c 51 #define GLUE_REG 0xa0140 52 #define GENERATION_DIVIDER_FORCE_REG 0xa0144 53 #define PCIE_REG0 0xa0120 54 #define LANE_ALIGN_REG0 0xa0124 55 #define SQUELCH_FFE_SETTING_REG 0xa0018 56 #define G1_SETTINGS_0_REG 0xa0034 57 #define G1_SETTINGS_1_REG 0xa0038 58 #define G1_SETTINGS_3_REG 0xa0440 59 #define G1_SETTINGS_4_REG 0xa0444 60 #define G2_SETTINGS_0_REG 0xa003c 61 #define G2_SETTINGS_1_REG 0xa0040 62 #define G2_SETTINGS_2_REG 0xa00f8 63 #define G2_SETTINGS_3_REG 0xa0448 64 #define G2_SETTINGS_4_REG 0xa044c 65 #define G3_SETTINGS_0_REG 0xa0044 66 #define G3_SETTINGS_1_REG 0xa0048 67 #define G3_SETTINGS_3_REG 0xa0450 68 #define G3_SETTINGS_4_REG 0xa0454 69 #define VTHIMPCAL_CTRL_REG 0xa0104 70 #define REF_REG0 0xa0134 71 #define CAL_REG6 0xa0168 72 #define RX_REG2 0xa0184 73 #define RX_REG3 0xa0188 74 #define PCIE_REG1 0xa0288 75 #define PCIE_REG3 0xa0290 76 #define LANE_CFG0_REG 0xa0600 77 #define LANE_CFG1_REG 0xa0604 78 #define LANE_CFG4_REG 0xa0620 79 #define LANE_CFG5_REG 0xa0624 80 #define GLOBAL_CLK_CTRL 0xa0704 81 #define GLOBAL_MISC_CTRL 0xa0718 82 #define GLOBAL_CLK_SRC_HI 0xa0710 83 84 #define GLOBAL_CLK_CTRL 0xa0704 85 #define GLOBAL_MISC_CTRL 0xa0718 86 #define GLOBAL_PM_CTRL 0xa0740 87 88 /* SATA registers */ 89 #define SATA_CTRL_REG_IND_ADDR 0xa80a0 90 #define SATA_CTRL_REG_IND_DATA 0xa80a4 91 92 #define SATA_VENDOR_PORT_0_REG_ADDR 0xa8178 93 #define SATA_VENDOR_PORT_1_REG_ADDR 0xa81f8 94 #define SATA_VENDOR_PORT_0_REG_DATA 0xa817c 95 #define SATA_VENDOR_PORT_1_REG_DATA 0xa81fc 96 97 /* Reference clock values and mask */ 98 #define POWER_AND_PLL_CTRL_REG_100MHZ_VAL 0x0 99 #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1 0x1 100 #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2 0x2 101 #define POWER_AND_PLL_CTRL_REG_40MHZ_VAL 0x3 102 #define GLOBAL_PM_CTRL_REG_25MHZ_VAL 0x7 103 #define GLOBAL_PM_CTRL_REG_40MHZ_VAL 0xc 104 #define LANE_CFG4_REG_25MHZ_VAL 0x200 105 #define LANE_CFG4_REG_40MHZ_VAL 0x300 106 107 #define POWER_AND_PLL_CTRL_REG_MASK (~(0x1f)) 108 #define GLOBAL_PM_CTRL_REG_MASK (~(0xff)) 109 #define LANE_CFG4_REG_MASK (~(0x1f00)) 110 111 #define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1 112 #define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1 113 #define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1 114 #define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1 115 #define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1) 116 117 #define MAX_SELECTOR_VAL 10 118 119 /* TWSI addresses */ 120 /* starting from A38x A0, i2c address of EEPROM is 0x57 */ 121 #define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \ 122 MV_88F68XX_Z1_ID ? 0x50 : 0x57) 123 #define RD_GET_MODE_ADDR 0x4c 124 #define DB_GET_MODE_SLM1363_ADDR 0x25 125 #define DB_GET_MODE_SLM1364_ADDR 0x24 126 #define DB381_GET_MODE_SLM1426_1427_ADDR 0x56 127 128 /* DB-BP Board 'SatR' mapping */ 129 #define SATR_DB_LANE1_MAX_OPTIONS 7 130 #define SATR_DB_LANE1_CFG_MASK 0x7 131 #define SATR_DB_LANE1_CFG_OFFSET 0 132 #define SATR_DB_LANE2_MAX_OPTIONS 4 133 #define SATR_DB_LANE2_CFG_MASK 0x38 134 #define SATR_DB_LANE2_CFG_OFFSET 3 135 136 /* GP Board 'SatR' mapping */ 137 #define SATR_GP_LANE1_CFG_MASK 0x4 138 #define SATR_GP_LANE1_CFG_OFFSET 2 139 #define SATR_GP_LANE2_CFG_MASK 0x8 140 #define SATR_GP_LANE2_CFG_OFFSET 3 141 142 /* For setting MPP2 and MPP3 to be TWSI mode and MPP 0,1 to UART mode */ 143 #define MPP_CTRL_REG 0x18000 144 #define MPP_SET_MASK (~(0xffff)) 145 #define MPP_SET_DATA (0x1111) 146 #define MPP_UART1_SET_MASK (~(0xff000)) 147 #define MPP_UART1_SET_DATA (0x66000) 148 149 #define DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS 0 150 /* DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS: Since address completion in 14bit 151 * address mode, and given that [14:8] => [19:13], the 2 lower bits [9:8] => 152 * [14:13] are dismissed. hence field offset is also shifted to 10 153 */ 154 #define DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS 10 155 156 #define RTC_MEMORY_CTRL_REG_BASE 0xE6000 157 #define RTC_MEMORY_WRAPPER_COUNT 8 158 #define RTC_MEMORY_WRAPPER_REG(i) (RTC_MEMORY_CTRL_REG_BASE + ((i) * 0x40)) 159 #define RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS 6 160 #define RTC_MEMORY_WRAPPER_CTRL_VAL (0x1 << RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS) 161 162 #define AVS_DEBUG_CNTR_REG 0xe4124 163 #define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073 164 165 #define AVS_ENABLED_CONTROL 0xe4130 166 #define AVS_LOW_VDD_LIMIT_OFFS 4 167 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) 168 #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) 169 #define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS) 170 171 #define AVS_HIGH_VDD_LIMIT_OFFS 12 172 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) 173 #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) 174 #define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS) 175 176 /* Board ID numbers */ 177 #define MARVELL_BOARD_ID_MASK 0x10 178 /* Customer boards for A38x */ 179 #define A38X_CUSTOMER_BOARD_ID_BASE 0x0 180 #define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0) 181 #define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1) 182 #define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2) 183 #define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \ 184 A38X_CUSTOMER_BOARD_ID_BASE) 185 186 /* Marvell boards for A38x */ 187 #define A38X_MARVELL_BOARD_ID_BASE 0x10 188 #define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0) 189 #define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1) 190 #define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2) 191 #define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3) 192 #define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4) 193 #define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5) 194 #define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6) 195 #define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7) 196 #define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \ 197 A38X_MARVELL_BOARD_ID_BASE) 198 199 /* Customer boards for A39x */ 200 #define A39X_CUSTOMER_BOARD_ID_BASE 0x20 201 #define A39X_CUSTOMER_BOARD_ID0 (A39X_CUSTOMER_BOARD_ID_BASE + 0) 202 #define A39X_CUSTOMER_BOARD_ID1 (A39X_CUSTOMER_BOARD_ID_BASE + 1) 203 #define A39X_MV_MAX_CUSTOMER_BOARD_ID (A39X_CUSTOMER_BOARD_ID_BASE + 2) 204 #define A39X_MV_CUSTOMER_BOARD_NUM (A39X_MV_MAX_CUSTOMER_BOARD_ID - \ 205 A39X_CUSTOMER_BOARD_ID_BASE) 206 207 /* Marvell boards for A39x */ 208 #define A39X_MARVELL_BOARD_ID_BASE 0x30 209 #define A39X_DB_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 0) 210 #define A39X_RD_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 1) 211 #define A39X_MV_MAX_MARVELL_BOARD_ID (A39X_MARVELL_BOARD_ID_BASE + 2) 212 #define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \ 213 A39X_MARVELL_BOARD_ID_BASE) 214 215 #define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE 216 #define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0 217 #define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1 218 #define MV_MAX_CUSTOMER_BOARD_ID A38X_MV_MAX_CUSTOMER_BOARD_ID 219 #define MV_CUSTOMER_BOARD_NUM A38X_MV_CUSTOMER_BOARD_NUM 220 #define MARVELL_BOARD_ID_BASE A38X_MARVELL_BOARD_ID_BASE 221 #define MV_MAX_MARVELL_BOARD_ID A38X_MV_MAX_MARVELL_BOARD_ID 222 #define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM 223 #define MV_DEFAULT_BOARD_ID DB_68XX_ID 224 #define MV_DEFAULT_DEVICE_ID MV_6811 225 226 #define MV_INVALID_BOARD_ID 0xffffffff 227 228 /* device revesion */ 229 #define DEV_VERSION_ID_REG 0x1823c 230 #define REVISON_ID_OFFS 8 231 #define REVISON_ID_MASK 0xf00 232 233 /* A38x revisions */ 234 #define MV_88F68XX_Z1_ID 0x0 235 #define MV_88F68XX_A0_ID 0x4 236 #define MV_88F68XX_B0_ID 0xa 237 /* A39x revisions */ 238 #define MV_88F69XX_Z1_ID 0x2 239 240 #define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) 241 #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) 242 #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) 243 #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) 244 #define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40)) 245 246 #define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8) 247 #define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \ 248 (MPP_REG_NUM(GPIO_NUM) * 8))); 249 #define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32) 250 #define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32) 251 252 /* device ID */ 253 /* Armada 38x Family */ 254 #define MV_6810_DEV_ID 0x6810 255 #define MV_6811_DEV_ID 0x6811 256 #define MV_6820_DEV_ID 0x6820 257 #define MV_6828_DEV_ID 0x6828 258 /* Armada 39x Family */ 259 #define MV_6920_DEV_ID 0x6920 260 #define MV_6928_DEV_ID 0x6928 261 262 enum { 263 MV_6810, 264 MV_6820, 265 MV_6811, 266 MV_6828, 267 MV_NONE, 268 MV_6920, 269 MV_6928, 270 MV_MAX_DEV_ID, 271 }; 272 273 #define MV_6820_INDEX 0 274 #define MV_6810_INDEX 1 275 #define MV_6811_INDEX 2 276 #define MV_6828_INDEX 3 277 278 #define MV_6920_INDEX 0 279 #define MV_6928_INDEX 1 280 281 #define MAX_DEV_ID_NUM 4 282 283 #define MV_6820_INDEX 0 284 #define MV_6810_INDEX 1 285 #define MV_6811_INDEX 2 286 #define MV_6828_INDEX 3 287 #define MV_6920_INDEX 0 288 #define MV_6928_INDEX 1 289 290 enum unit_id { 291 PEX_UNIT_ID, 292 ETH_GIG_UNIT_ID, 293 USB3H_UNIT_ID, 294 USB3D_UNIT_ID, 295 SATA_UNIT_ID, 296 QSGMII_UNIT_ID, 297 XAUI_UNIT_ID, 298 RXAUI_UNIT_ID, 299 MAX_UNITS_ID 300 }; 301 302 struct board_wakeup_gpio { 303 u32 board_id; 304 int gpio_num; 305 }; 306 307 enum suspend_wakeup_status { 308 SUSPEND_WAKEUP_DISABLED, 309 SUSPEND_WAKEUP_ENABLED, 310 SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED, 311 }; 312 313 /* 314 * GPIO status indication for Suspend Wakeup: 315 * If suspend to RAM is supported and GPIO inidcation is implemented, 316 * set the gpio number 317 * If suspend to RAM is supported but GPIO indication is not implemented 318 * set '-2' 319 * If suspend to RAM is not supported set '-1' 320 */ 321 #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT 322 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 323 {A38X_CUSTOMER_BOARD_ID0, -1 }, \ 324 {A38X_CUSTOMER_BOARD_ID0, -1 }, \ 325 }; 326 327 #else 328 329 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 330 {RD_NAS_68XX_ID, -2 }, \ 331 {DB_68XX_ID, -1 }, \ 332 {RD_AP_68XX_ID, -2 }, \ 333 {DB_AP_68XX_ID, -2 }, \ 334 {DB_GP_68XX_ID, -2 }, \ 335 {DB_BP_6821_ID, -2 }, \ 336 {DB_AMC_6820_ID, -2 }, \ 337 }; 338 #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ 339 340 u32 mv_board_tclk_get(void); 341 u32 mv_board_id_get(void); 342 u32 mv_board_id_index_get(u32 board_id); 343 u32 sys_env_unit_max_num_get(enum unit_id unit); 344 enum suspend_wakeup_status sys_env_suspend_wakeup_check(void); 345 u8 sys_env_device_rev_get(void); 346 u32 sys_env_device_id_get(void); 347 u16 sys_env_model_get(void); 348 struct dlb_config *sys_env_dlb_config_ptr_get(void); 349 u32 sys_env_get_cs_ena_from_reg(void); 350 351 #endif /* _SYS_ENV_LIB_H */ 352