1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7
8 #include <common.h>
9 #include <asm/armv8/mmu.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/arch/board.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 #define OTX_MEM_MAP_USED 3
17
18 /* 1 for 83xx, +1 is end of list which needs to be empty */
19 #define OTX_MEM_MAP_MAX (OTX_MEM_MAP_USED + 1 + CONFIG_NR_DRAM_BANKS + 1)
20
21 static struct mm_region otx_mem_map[OTX_MEM_MAP_MAX] = {
22 {
23 .virt = 0x800000000000UL,
24 .phys = 0x800000000000UL,
25 .size = 0x40000000000UL,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 PTE_BLOCK_NON_SHARE
28 }, {
29 .virt = 0x840000000000UL,
30 .phys = 0x840000000000UL,
31 .size = 0x40000000000UL,
32 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
33 PTE_BLOCK_NON_SHARE
34 }, {
35 .virt = 0x880000000000UL,
36 .phys = 0x880000000000UL,
37 .size = 0x40000000000UL,
38 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
39 PTE_BLOCK_NON_SHARE
40 }
41
42 };
43
44 struct mm_region *mem_map = otx_mem_map;
45
mem_map_fill(void)46 void mem_map_fill(void)
47 {
48 int banks = OTX_MEM_MAP_USED;
49 u32 dram_start = CONFIG_SYS_TEXT_BASE;
50
51 if (otx_is_soc(CN83XX)) {
52 otx_mem_map[banks].virt = 0x8c0000000000UL;
53 otx_mem_map[banks].phys = 0x8c0000000000UL;
54 otx_mem_map[banks].size = 0x40000000000UL;
55 otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
56 PTE_BLOCK_NON_SHARE;
57 banks = banks + 1;
58 }
59
60 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
61 otx_mem_map[banks].virt = dram_start;
62 otx_mem_map[banks].phys = dram_start;
63 otx_mem_map[banks].size = gd->ram_size;
64 otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
65 PTE_BLOCK_NON_SHARE;
66 banks = banks + 1;
67 }
68 }
69
get_page_table_size(void)70 u64 get_page_table_size(void)
71 {
72 return 0x80000;
73 }
74
reset_cpu(ulong addr)75 void reset_cpu(ulong addr)
76 {
77 }
78