1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * Common functions for OMAP4/5 based boards 5 * 6 * (C) Copyright 2010 7 * Texas Instruments, <www.ti.com> 8 * 9 * Author : 10 * Aneesh V <aneesh@ti.com> 11 * Steve Sakoman <steve@sakoman.com> 12 */ 13 14 #include <common.h> 15 #include <cpu_func.h> 16 #include <log.h> 17 #include <asm/cache.h> 18 #include <asm/global_data.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* 23 * Without LPAE short descriptors are used 24 * Set C - Cache Bit3 25 * Set B - Buffer Bit2 26 * The last 2 bits set to 0b10 27 * Do Not set XN bit4 28 * So value is 0xe 29 * 30 * With LPAE cache configuration happens via MAIR0 register 31 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. 32 * 0xFF maps to Cache writeback with Read and Write Allocate set 33 * The bits[1:0] should have the value 0b01 for the first level 34 * descriptor. 35 * So the value is 0xd 36 */ 37 38 #ifdef CONFIG_ARMV7_LPAE 39 #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC 40 #else 41 #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK 42 #endif 43 44 #define ARMV7_DOMAIN_CLIENT 1 45 #define ARMV7_DOMAIN_MASK (0x3 << 0) 46 enable_caches(void)47void enable_caches(void) 48 { 49 50 /* Enable I cache if not enabled */ 51 if (!icache_status()) 52 icache_enable(); 53 54 dcache_enable(); 55 } 56 dram_bank_mmu_setup(int bank)57void dram_bank_mmu_setup(int bank) 58 { 59 struct bd_info *bd = gd->bd; 60 int i; 61 62 u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; 63 u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; 64 u32 end = start + size; 65 66 debug("%s: bank: %d\n", __func__, bank); 67 for (i = start; i < end; i++) 68 set_section_dcache(i, ARMV7_DCACHE_POLICY); 69 } 70 arm_init_domains(void)71void arm_init_domains(void) 72 { 73 u32 reg; 74 75 reg = get_dacr(); 76 /* 77 * Set DOMAIN to client access so that all permissions 78 * set in pagetables are validated by the mmu. 79 */ 80 reg &= ~ARMV7_DOMAIN_MASK; 81 reg |= ARMV7_DOMAIN_CLIENT; 82 set_dacr(reg); 83 } 84