1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
4  *
5  * Based on original Kirkwood support which is
6  * (C) Copyright 2009
7  * Marvell Semiconductor <www.marvell.com>
8  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9  */
10 
11 #include <common.h>
12 #include <config.h>
13 #include <init.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/global_data.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 /*
20  * orion5x_sdram_bar - reads SDRAM Base Address Register
21  */
orion5x_sdram_bar(enum memory_bank bank)22 u32 orion5x_sdram_bar(enum memory_bank bank)
23 {
24 	struct orion5x_ddr_addr_decode_registers *winregs =
25 		(struct orion5x_ddr_addr_decode_registers *)
26 		ORION5X_DRAM_BASE;
27 
28 	u32 result = 0;
29 	u32 enable = 0x01 & winregs[bank].size;
30 
31 	if ((!enable) || (bank > BANK3))
32 		return 0;
33 
34 	result = winregs[bank].base;
35 	return result;
36 }
dram_init(void)37 int dram_init (void)
38 {
39 	/* dram_init must store complete ramsize in gd->ram_size */
40 	gd->ram_size = get_ram_size(
41 			(long *) orion5x_sdram_bar(0),
42 			CONFIG_MAX_RAM_BANK_SIZE);
43 	return 0;
44 }
45 
dram_init_banksize(void)46 int dram_init_banksize(void)
47 {
48 	int i;
49 
50 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
51 		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
52 		gd->bd->bi_dram[i].size = get_ram_size(
53 			(long *) (gd->bd->bi_dram[i].start),
54 			CONFIG_MAX_RAM_BANK_SIZE);
55 	}
56 
57 	return 0;
58 }
59