1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4  */
5 #include <init.h>
6 #include <asm/io.h>
7 #include <asm/arch-rockchip/bootrom.h>
8 #include <asm/arch-rockchip/grf_rk322x.h>
9 #include <asm/arch-rockchip/hardware.h>
10 
11 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
12 	[BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000",
13 	[BROM_BOOTSOURCE_SD] = "/dwmmc@30000000",
14 };
15 
16 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)17 void board_debug_uart_init(void)
18 {
19 #define GRF_BASE	0x11000000
20 	static struct rk322x_grf * const grf = (void *)GRF_BASE;
21 	enum {
22 		GPIO1B2_SHIFT		= 4,
23 		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
24 		GPIO1B2_GPIO            = 0,
25 		GPIO1B2_UART1_SIN,
26 		GPIO1B2_UART21_SIN,
27 
28 		GPIO1B1_SHIFT		= 2,
29 		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
30 		GPIO1B1_GPIO            = 0,
31 		GPIO1B1_UART1_SOUT,
32 		GPIO1B1_UART21_SOUT,
33 	};
34 	enum {
35 		CON_IOMUX_UART2SEL_SHIFT = 8,
36 		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
37 		CON_IOMUX_UART2SEL_2	= 0,
38 		CON_IOMUX_UART2SEL_21,
39 	};
40 
41 	/* Enable early UART2 channel 1 on the RK322x */
42 	rk_clrsetreg(&grf->gpio1b_iomux,
43 		     GPIO1B1_MASK | GPIO1B2_MASK,
44 		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
45 		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
46 	/* Set channel C as UART2 input */
47 	rk_clrsetreg(&grf->con_iomux,
48 		     CON_IOMUX_UART2SEL_MASK,
49 		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
50 }
51 #endif
52 
arch_cpu_init(void)53 int arch_cpu_init(void)
54 {
55 #ifdef CONFIG_SPL_BUILD
56 #define SGRF_BASE	0x10150000
57 	static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE;
58 
59 	/* Disable the ddr secure region setting to make it non-secure */
60 	rk_clrreg(&sgrf->soc_con[0], 0x4000);
61 #else
62 #define GRF_BASE	0x11000000
63 	static struct rk322x_grf * const grf = (void *)GRF_BASE;
64 	/*
65 	 * The integrated macphy is enabled by default, disable it
66 	 * for saving power consuming.
67 	 */
68 	rk_clrsetreg(&grf->macphy_con[0],
69 		     MACPHY_CFG_ENABLE_MASK,
70 		     0 << MACPHY_CFG_ENABLE_SHIFT);
71 
72 #endif
73 	return 0;
74 }
75