1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *Copyright (c) 2018 Rockchip Electronics Co., Ltd
4 */
5 #include <common.h>
6 #include <init.h>
7 #include <malloc.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include <asm/arch/grf_rk3308.h>
11 #include <asm/arch-rockchip/hardware.h>
12 #include <asm/gpio.h>
13 #include <debug_uart.h>
14 #include <linux/bitops.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #include <asm/armv8/mmu.h>
19 static struct mm_region rk3308_mem_map[] = {
20 {
21 .virt = 0x0UL,
22 .phys = 0x0UL,
23 .size = 0xff000000UL,
24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
25 PTE_BLOCK_INNER_SHARE
26 }, {
27 .virt = 0xff000000UL,
28 .phys = 0xff000000UL,
29 .size = 0x01000000UL,
30 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
31 PTE_BLOCK_NON_SHARE |
32 PTE_BLOCK_PXN | PTE_BLOCK_UXN
33 }, {
34 /* List terminator */
35 0,
36 }
37 };
38
39 struct mm_region *mem_map = rk3308_mem_map;
40
41 #define GRF_BASE 0xff000000
42 #define SGRF_BASE 0xff2b0000
43
44 enum {
45 GPIO1C7_SHIFT = 8,
46 GPIO1C7_MASK = GENMASK(11, 8),
47 GPIO1C7_GPIO = 0,
48 GPIO1C7_UART1_RTSN,
49 GPIO1C7_UART2_TX_M0,
50 GPIO1C7_SPI2_MOSI,
51 GPIO1C7_JTAG_TMS,
52
53 GPIO1C6_SHIFT = 4,
54 GPIO1C6_MASK = GENMASK(7, 4),
55 GPIO1C6_GPIO = 0,
56 GPIO1C6_UART1_CTSN,
57 GPIO1C6_UART2_RX_M0,
58 GPIO1C6_SPI2_MISO,
59 GPIO1C6_JTAG_TCLK,
60
61 GPIO4D3_SHIFT = 6,
62 GPIO4D3_MASK = GENMASK(7, 6),
63 GPIO4D3_GPIO = 0,
64 GPIO4D3_SDMMC_D3,
65 GPIO4D3_UART2_TX_M1,
66
67 GPIO4D2_SHIFT = 4,
68 GPIO4D2_MASK = GENMASK(5, 4),
69 GPIO4D2_GPIO = 0,
70 GPIO4D2_SDMMC_D2,
71 GPIO4D2_UART2_RX_M1,
72
73 UART2_IO_SEL_SHIFT = 2,
74 UART2_IO_SEL_MASK = GENMASK(3, 2),
75 UART2_IO_SEL_M0 = 0,
76 UART2_IO_SEL_M1,
77 UART2_IO_SEL_USB,
78
79 GPIO2C0_SEL_SRC_CTRL_SHIFT = 11,
80 GPIO2C0_SEL_SRC_CTRL_MASK = BIT(11),
81 GPIO2C0_SEL_SRC_CTRL_IOMUX = 0,
82 GPIO2C0_SEL_SRC_CTRL_SEL_PLUS,
83
84 GPIO3B3_SEL_SRC_CTRL_SHIFT = 7,
85 GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7),
86 GPIO3B3_SEL_SRC_CTRL_IOMUX = 0,
87 GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
88
89 GPIO3B3_SEL_PLUS_SHIFT = 4,
90 GPIO3B3_SEL_PLUS_MASK = GENMASK(6, 4),
91 GPIO3B3_SEL_PLUS_GPIO3_B3 = 0,
92 GPIO3B3_SEL_PLUS_FLASH_ALE,
93 GPIO3B3_SEL_PLUS_EMMC_PWREN,
94 GPIO3B3_SEL_PLUS_SPI1_CLK,
95 GPIO3B3_SEL_PLUS_LCDC_D23_M1,
96
97 GPIO3B2_SEL_SRC_CTRL_SHIFT = 3,
98 GPIO3B2_SEL_SRC_CTRL_MASK = BIT(3),
99 GPIO3B2_SEL_SRC_CTRL_IOMUX = 0,
100 GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
101
102 GPIO3B2_SEL_PLUS_SHIFT = 0,
103 GPIO3B2_SEL_PLUS_MASK = GENMASK(2, 0),
104 GPIO3B2_SEL_PLUS_GPIO3_B2 = 0,
105 GPIO3B2_SEL_PLUS_FLASH_RDN,
106 GPIO3B2_SEL_PLUS_EMMC_RSTN,
107 GPIO3B2_SEL_PLUS_SPI1_MISO,
108 GPIO3B2_SEL_PLUS_LCDC_D22_M1,
109
110 I2C3_IOFUNC_SRC_CTRL_SHIFT = 10,
111 I2C3_IOFUNC_SRC_CTRL_MASK = BIT(10),
112 I2C3_IOFUNC_SRC_CTRL_SEL_PLUS = 1,
113
114 GPIO2A3_SEL_SRC_CTRL_SHIFT = 7,
115 GPIO2A3_SEL_SRC_CTRL_MASK = BIT(7),
116 GPIO2A3_SEL_SRC_CTRL_SEL_PLUS = 1,
117
118 GPIO2A2_SEL_SRC_CTRL_SHIFT = 3,
119 GPIO2A2_SEL_SRC_CTRL_MASK = BIT(3),
120 GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1,
121 };
122
123 enum {
124 IOVSEL3_CTRL_SHIFT = 8,
125 IOVSEL3_CTRL_MASK = BIT(8),
126 VCCIO3_SEL_BY_GPIO = 0,
127 VCCIO3_SEL_BY_IOVSEL3,
128
129 IOVSEL3_SHIFT = 3,
130 IOVSEL3_MASK = BIT(3),
131 VCCIO3_3V3 = 0,
132 VCCIO3_1V8,
133 };
134
135 /*
136 * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
137 * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
138 * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
139 * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
140 * for other usage.
141 */
142
143 #define GPIO0_A4 4
144
rk_board_init(void)145 int rk_board_init(void)
146 {
147 static struct rk3308_grf * const grf = (void *)GRF_BASE;
148 u32 val;
149 int ret;
150
151 ret = gpio_request(GPIO0_A4, "gpio0_a4");
152 if (ret < 0) {
153 printf("request for gpio0_a4 failed:%d\n", ret);
154 return 0;
155 }
156
157 gpio_direction_input(GPIO0_A4);
158
159 if (gpio_get_value(GPIO0_A4))
160 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
161 VCCIO3_1V8 << IOVSEL3_SHIFT;
162 else
163 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
164 VCCIO3_3V3 << IOVSEL3_SHIFT;
165 rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
166
167 gpio_free(GPIO0_A4);
168 return 0;
169 }
170
171 #if defined(CONFIG_DEBUG_UART)
board_debug_uart_init(void)172 __weak void board_debug_uart_init(void)
173 {
174 static struct rk3308_grf * const grf = (void *)GRF_BASE;
175
176 /* Enable early UART2 channel m1 on the rk3308 */
177 rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
178 UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
179 rk_clrsetreg(&grf->gpio4d_iomux,
180 GPIO4D3_MASK | GPIO4D2_MASK,
181 GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
182 GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
183 }
184 #endif
185
186 #if defined(CONFIG_SPL_BUILD)
arch_cpu_init(void)187 int arch_cpu_init(void)
188 {
189 static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
190 static struct rk3308_grf * const grf = (void *)GRF_BASE;
191
192 /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
193 rk_clrreg(&sgrf->con_secure0, 0x2b83);
194
195 /*
196 * Enable plus options to use more pinctrl functions, including
197 * GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS.
198 */
199 rk_clrsetreg(&grf->soc_con13,
200 I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK |
201 GPIO2A2_SEL_SRC_CTRL_MASK,
202 I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT |
203 GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT |
204 GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT);
205
206 /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */
207 rk_clrsetreg(&grf->soc_con15,
208 GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK |
209 GPIO3B2_SEL_SRC_CTRL_MASK,
210 GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT |
211 GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT |
212 GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT);
213
214 return 0;
215 }
216 #endif
217