1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 * Copyright (c) 2016 Andreas Färber
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <syscon.h>
10 #include <asm/armv8/mmu.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch-rockchip/bootrom.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cru_rk3368.h>
16 #include <asm/arch-rockchip/grf_rk3368.h>
17 #include <asm/arch-rockchip/hardware.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #define IMEM_BASE 0xFF8C0000
24
25 /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
26 #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4)
27 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
28 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
29 /* exsram may using by mcu to accessing dram(0x0-0x20000000) */
30 #define MCU_EXSRAM_BASE (0)
31 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
32 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
33 /* experi no used, reserved value = 0 */
34 #define MCU_EXPERI_BASE (0)
35 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
36 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
37
38 static struct mm_region rk3368_mem_map[] = {
39 {
40 .virt = 0x0UL,
41 .phys = 0x0UL,
42 .size = 0x80000000UL,
43 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
44 PTE_BLOCK_INNER_SHARE
45 }, {
46 .virt = 0xf0000000UL,
47 .phys = 0xf0000000UL,
48 .size = 0x10000000UL,
49 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
50 PTE_BLOCK_NON_SHARE |
51 PTE_BLOCK_PXN | PTE_BLOCK_UXN
52 }, {
53 /* List terminator */
54 0,
55 }
56 };
57
58 struct mm_region *mem_map = rk3368_mem_map;
59
60 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
61 [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
62 [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
63 };
64
65 #ifdef CONFIG_ARCH_EARLY_INIT_R
mcu_init(void)66 static int mcu_init(void)
67 {
68 struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
69 struct rk3368_cru *cru = rockchip_get_cru();
70
71 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
72 MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
73 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
74 MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
75 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
76 MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
77 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
78 MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
79 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
80 MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
81 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
82 MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
83
84 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
85 (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
86 (5 << MCU_CLK_DIV_SHIFT));
87
88 /* mcu dereset, for start running */
89 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
90
91 return 0;
92 }
93
arch_early_init_r(void)94 int arch_early_init_r(void)
95 {
96 return mcu_init();
97 }
98 #endif
99
100 #ifdef CONFIG_SPL_BUILD
101 /*
102 * The SPL (and also the full U-Boot stage on the RK3368) will run in
103 * secure mode (i.e. EL3) and an ATF will eventually be booted before
104 * starting up the operating system... so we can initialize the SGRF
105 * here and rely on the ATF installing the final (secure) policy
106 * later.
107 */
sgrf_soc_con_addr(unsigned int no)108 static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
109 {
110 const uintptr_t SGRF_BASE =
111 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
112
113 return SGRF_BASE + sizeof(u32) * no;
114 }
115
sgrf_busdmac_addr(unsigned int no)116 static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
117 {
118 const uintptr_t SGRF_BASE =
119 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
120 const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
121 const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
122
123 return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
124 }
125
sgrf_init(void)126 static void sgrf_init(void)
127 {
128 struct rk3368_cru * const cru =
129 (struct rk3368_cru * const)rockchip_get_cru();
130 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
131 const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
132 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
133
134 /* Set all configurable IP to 'non secure'-mode */
135 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
136 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
137 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
138
139 /*
140 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
141 * Original comment: "ddr space set no secure mode"
142 */
143 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
144 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
145 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
146
147 /* Set 'secure dma' to 'non secure'-mode */
148 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
149 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
150
151 dsb(); /* barrier */
152
153 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
154 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
155
156 dsb(); /* barrier */
157 udelay(10);
158
159 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
160 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
161 }
162
arch_cpu_init(void)163 int arch_cpu_init(void)
164 {
165 /* Reset security, so we can use DMA in the MMC drivers */
166 sgrf_init();
167
168 return 0;
169 }
170 #endif
171
172 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)173 void board_debug_uart_init(void)
174 {
175 /*
176 * N.B.: This is called before the device-model has been
177 * initialised. For this reason, we can not access
178 * the GRF address range using the syscon API.
179 */
180 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
181 struct rk3368_grf * const grf =
182 (struct rk3368_grf * const)0xff770000;
183
184 enum {
185 GPIO2D1_MASK = GENMASK(3, 2),
186 GPIO2D1_GPIO = 0,
187 GPIO2D1_UART0_SOUT = (1 << 2),
188
189 GPIO2D0_MASK = GENMASK(1, 0),
190 GPIO2D0_GPIO = 0,
191 GPIO2D0_UART0_SIN = (1 << 0),
192 };
193
194 /* Enable early UART0 on the RK3368 */
195 rk_clrsetreg(&grf->gpio2d_iomux,
196 GPIO2D0_MASK, GPIO2D0_UART0_SIN);
197 rk_clrsetreg(&grf->gpio2d_iomux,
198 GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
199 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
200 struct rk3368_pmu_grf * const pmugrf __maybe_unused =
201 (struct rk3368_pmu_grf * const)0xff738000;
202
203 enum {
204 /* UART4 */
205 GPIO0D2_MASK = GENMASK(5, 4),
206 GPIO0D2_GPIO = 0,
207 GPIO0D2_UART4_SOUT = (3 << 4),
208
209 GPIO0D3_MASK = GENMASK(7, 6),
210 GPIO0D3_GPIO = 0,
211 GPIO0D3_UART4_SIN = (3 << 6),
212 };
213
214 /* Enable early UART4 on the PX5 */
215 rk_clrsetreg(&pmugrf->gpio0d_iomux,
216 GPIO0D2_MASK | GPIO0D3_MASK,
217 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
218 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
219 struct rk3368_grf * const grf =
220 (struct rk3368_grf * const)0xff770000;
221
222 enum {
223 GPIO2A6_SHIFT = 12,
224 GPIO2A6_MASK = GENMASK(13, 12),
225 GPIO2A6_GPIO = 0,
226 GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
227
228 GPIO2A5_SHIFT = 10,
229 GPIO2A5_MASK = GENMASK(11, 10),
230 GPIO2A5_GPIO = 0,
231 GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
232 };
233
234 /* Enable early UART2 on the RK3368 */
235 rk_clrsetreg(&grf->gpio2a_iomux,
236 GPIO2A6_MASK, GPIO2A6_UART2_SIN);
237 rk_clrsetreg(&grf->gpio2a_iomux,
238 GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
239 #endif
240 }
241 #endif
242