1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4  */
5 
6 #ifndef _CLOCK_MANAGER_H_
7 #define _CLOCK_MANAGER_H_
8 
9 phys_addr_t socfpga_get_clkmgr_addr(void);
10 
11 #ifndef __ASSEMBLY__
12 void cm_wait_for_lock(u32 mask);
13 int cm_wait_for_fsm(void);
14 void cm_print_clock_quick_summary(void);
15 #endif
16 
17 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
18 #include <asm/arch/clock_manager_gen5.h>
19 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
20 #include <asm/arch/clock_manager_arria10.h>
21 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
22 #include <asm/arch/clock_manager_s10.h>
23 #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
24 #include <asm/arch/clock_manager_agilex.h>
25 #endif
26 
27 #endif /* _CLOCK_MANAGER_H_ */
28