1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2016-2017 Intel Corporation
4  */
5 
6 #ifndef _SOCFPGA_MISC_H_
7 #define _SOCFPGA_MISC_H_
8 
9 #include <asm/sections.h>
10 
11 void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
12 
13 struct bsel {
14 	const char	*mode;
15 	const char	*name;
16 };
17 
18 extern struct bsel bsel_str[];
19 
20 #ifdef CONFIG_FPGA
21 void socfpga_fpga_add(void *fpga_desc);
22 #else
socfpga_fpga_add(void * fpga_desc)23 static inline void socfpga_fpga_add(void *fpga_desc) {}
24 #endif
25 
26 #ifdef CONFIG_TARGET_SOCFPGA_GEN5
27 void socfpga_sdram_remap_zero(void);
socfpga_is_booting_from_fpga(void)28 static inline bool socfpga_is_booting_from_fpga(void)
29 {
30 	if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
31 	    (__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
32 		return true;
33 	return false;
34 }
35 #endif
36 
37 #ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
38 void socfpga_init_security_policies(void);
39 void socfpga_sdram_remap_zero(void);
40 #endif
41 
42 #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
43 	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
44 int is_fpga_config_ready(void);
45 #endif
46 
47 void do_bridge_reset(int enable, unsigned int mask);
48 void socfpga_pl310_clear(void);
49 void socfpga_get_managers_addr(void);
50 
51 #endif /* _SOCFPGA_MISC_H_ */
52