1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016-2017 Intel Corporation
4 */
5
6 #include <altera.h>
7 #include <common.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <init.h>
11 #include <miiphy.h>
12 #include <netdev.h>
13 #include <ns16550.h>
14 #include <watchdog.h>
15 #include <asm/arch/misc.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/reset_manager.h>
18 #include <asm/arch/reset_manager_arria10.h>
19 #include <asm/arch/sdram_arria10.h>
20 #include <asm/arch/system_manager.h>
21 #include <asm/arch/nic301.h>
22 #include <asm/io.h>
23 #include <asm/pl310.h>
24
25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
27 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
30 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
31
32 /*
33 * FPGA programming support for SoC FPGA Arria 10
34 */
35 static Altera_desc altera_fpga[] = {
36 {
37 /* Family */
38 Altera_SoCFPGA,
39 /* Interface type */
40 fast_passive_parallel,
41 /* No limitation as additional data will be ignored */
42 -1,
43 /* No device function table */
44 NULL,
45 /* Base interface address specified in driver */
46 NULL,
47 /* No cookie implementation */
48 0
49 },
50 };
51
52 #if defined(CONFIG_SPL_BUILD)
53 static struct pl310_regs *const pl310 =
54 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
55 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
56 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
57
58 /*
59 + * This function initializes security policies to be consistent across
60 + * all logic units in the Arria 10.
61 + *
62 + * The idea is to set all security policies to be normal, nonsecure
63 + * for all units.
64 + */
socfpga_init_security_policies(void)65 void socfpga_init_security_policies(void)
66 {
67 /* Put OCRAM in non-secure */
68 writel(0x003f0000, &noc_fw_ocram_base->region0);
69 writel(0x1, &noc_fw_ocram_base->enable);
70
71 /* Put DDR in non-secure */
72 writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
73 writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
74
75 /* Enable priviledged and non-priviledged access to L4 peripherals */
76 writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
77
78 /* Enable secure and non-secure transactions to bridges */
79 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
80 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
81
82 writel(0x0007FFFF,
83 socfpga_get_sysmgr_addr() + SYSMGR_A10_ECC_INTMASK_SET);
84 }
85
socfpga_sdram_remap_zero(void)86 void socfpga_sdram_remap_zero(void)
87 {
88 /* Configure the L2 controller to make SDRAM start at 0 */
89 writel(0x1, &pl310->pl310_addr_filter_start);
90 }
91 #endif
92
arch_early_init_r(void)93 int arch_early_init_r(void)
94 {
95 /* Add device descriptor to FPGA device table */
96 socfpga_fpga_add(&altera_fpga[0]);
97
98 return 0;
99 }
100
101 /*
102 * Print CPU information
103 */
104 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)105 int print_cpuinfo(void)
106 {
107 const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
108 SYSMGR_A10_BOOTINFO);
109 const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
110
111 puts("CPU: Altera SoCFPGA Arria 10\n");
112
113 printf("BOOT: %s\n", bsel_str[bsel].name);
114 return 0;
115 }
116 #endif
117
do_bridge_reset(int enable,unsigned int mask)118 void do_bridge_reset(int enable, unsigned int mask)
119 {
120 if (enable)
121 socfpga_reset_deassert_bridges_handoff();
122 else
123 socfpga_bridges_reset();
124 }
125