1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4 *
5 */
6
7 #include <common.h>
8 #include <hang.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/smc_api.h>
13 #include <asm/arch/system_manager.h>
14 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
15 #include <linux/iopoll.h>
16 #include <linux/intel-smc.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /* Assert or de-assert SoCFPGA reset manager reset. */
socfpga_per_reset(u32 reset,int set)21 void socfpga_per_reset(u32 reset, int set)
22 {
23 unsigned long reg;
24
25 if (RSTMGR_BANK(reset) == 0)
26 reg = RSTMGR_SOC64_MPUMODRST;
27 else if (RSTMGR_BANK(reset) == 1)
28 reg = RSTMGR_SOC64_PER0MODRST;
29 else if (RSTMGR_BANK(reset) == 2)
30 reg = RSTMGR_SOC64_PER1MODRST;
31 else if (RSTMGR_BANK(reset) == 3)
32 reg = RSTMGR_SOC64_BRGMODRST;
33 else /* Invalid reset register, do nothing */
34 return;
35
36 if (set)
37 setbits_le32(socfpga_get_rstmgr_addr() + reg,
38 1 << RSTMGR_RESET(reset));
39 else
40 clrbits_le32(socfpga_get_rstmgr_addr() + reg,
41 1 << RSTMGR_RESET(reset));
42 }
43
44 /*
45 * Assert reset on every peripheral but L4WD0.
46 * Watchdog must be kept intact to prevent glitches
47 * and/or hangs.
48 */
socfpga_per_reset_all(void)49 void socfpga_per_reset_all(void)
50 {
51 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
52
53 /* disable all except OCP and l4wd0. OCP disable later */
54 writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
55 socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
56 writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
57 writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
58 }
59
socfpga_bridges_reset(int enable)60 void socfpga_bridges_reset(int enable)
61 {
62 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
63 u64 arg = enable;
64
65 int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
66 if (ret) {
67 printf("SMC call failed with error %d in %s.\n", ret, __func__);
68 return;
69 }
70 #else
71 u32 reg;
72
73 if (enable) {
74 /* clear idle request to all bridges */
75 setbits_le32(socfpga_get_sysmgr_addr() +
76 SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
77
78 /* Release all bridges from reset state */
79 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
80 ~0);
81
82 /* Poll until all idleack to 0 */
83 read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
84 SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
85 300000);
86 } else {
87 /* set idle request to all bridges */
88 writel(~0,
89 socfpga_get_sysmgr_addr() +
90 SYSMGR_SOC64_NOC_IDLEREQ_SET);
91
92 /* Enable the NOC timeout */
93 writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
94
95 /* Poll until all idleack to 1 */
96 read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
97 SYSMGR_SOC64_NOC_IDLEACK, reg,
98 reg == (SYSMGR_NOC_H2F_MSK |
99 SYSMGR_NOC_LWH2F_MSK),
100 1000, 300000);
101
102 /* Poll until all idlestatus to 1 */
103 read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
104 SYSMGR_SOC64_NOC_IDLESTATUS, reg,
105 reg == (SYSMGR_NOC_H2F_MSK |
106 SYSMGR_NOC_LWH2F_MSK),
107 1000, 300000);
108
109 /* Reset all bridges (except NOR DDR scheduler & F2S) */
110 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
111 ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
112 RSTMGR_BRGMODRST_FPGA2SOC_MASK));
113
114 /* Disable NOC timeout */
115 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
116 }
117 #endif
118 }
119
120 /*
121 * Return non-zero if the CPU has been warm reset
122 */
cpu_has_been_warmreset(void)123 int cpu_has_been_warmreset(void)
124 {
125 return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
126 RSTMGR_L4WD_MPU_WARMRESET_MASK;
127 }
128
print_reset_info(void)129 void print_reset_info(void)
130 {
131 bool iswd;
132 int n;
133 u32 stat = cpu_has_been_warmreset();
134
135 printf("Reset state: %s%s", stat ? "Warm " : "Cold",
136 (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
137
138 stat &= ~RSTMGR_STAT_SDMWARMRST;
139 if (!stat) {
140 puts("\n");
141 return;
142 }
143
144 n = generic_ffs(stat) - 1;
145 iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
146 printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
147 iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
148 (n - RSTMGR_STAT_MPU0RST_BITPOS));
149 }
150