1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4 *
5 */
6
7 #include <hang.h>
8 #include <init.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/u-boot.h>
13 #include <asm/utils.h>
14 #include <common.h>
15 #include <debug_uart.h>
16 #include <image.h>
17 #include <spl.h>
18 #include <asm/arch/clock_manager.h>
19 #include <asm/arch/firewall.h>
20 #include <asm/arch/mailbox_s10.h>
21 #include <asm/arch/misc.h>
22 #include <asm/arch/reset_manager.h>
23 #include <asm/arch/system_manager.h>
24 #include <watchdog.h>
25 #include <dm/uclass.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
spl_boot_device(void)29 u32 spl_boot_device(void)
30 {
31 /* TODO: Get from SDM or handoff */
32 return BOOT_DEVICE_MMC1;
33 }
34
35 #ifdef CONFIG_SPL_MMC_SUPPORT
spl_mmc_boot_mode(const u32 boot_device)36 u32 spl_mmc_boot_mode(const u32 boot_device)
37 {
38 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
39 return MMCSD_MODE_FS;
40 #else
41 return MMCSD_MODE_RAW;
42 #endif
43 }
44 #endif
45
board_init_f(ulong dummy)46 void board_init_f(ulong dummy)
47 {
48 const struct cm_config *cm_default_cfg = cm_get_default_config();
49 int ret;
50
51 ret = spl_early_init();
52 if (ret)
53 hang();
54
55 socfpga_get_managers_addr();
56
57 /* Ensure watchdog is paused when debugging is happening */
58 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
59 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
60
61 #ifdef CONFIG_HW_WATCHDOG
62 /* Enable watchdog before initializing the HW */
63 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
64 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
65 hw_watchdog_init();
66 #endif
67
68 /* ensure all processors are not released prior Linux boot */
69 writeq(0, CPU_RELEASE_ADDR);
70
71 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
72 timer_init();
73
74 sysmgr_pinmux_init();
75
76 /* configuring the HPS clocks */
77 cm_basic_init(cm_default_cfg);
78
79 #ifdef CONFIG_DEBUG_UART
80 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
81 debug_uart_init();
82 #endif
83
84 preloader_console_init();
85 print_reset_info();
86 cm_print_clock_quick_summary();
87
88 firewall_setup();
89
90 /* disable ocram security at CCU for non secure access */
91 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
92 CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
93 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
94 CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
95
96 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
97 struct udevice *dev;
98
99 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
100 if (ret) {
101 debug("DRAM init failed: %d\n", ret);
102 hang();
103 }
104 #endif
105
106 mbox_init();
107
108 #ifdef CONFIG_CADENCE_QSPI
109 mbox_qspi_open();
110 #endif
111 }
112