1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * sun6i specific clock code
4 *
5 * (C) Copyright 2007-2012
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
10 */
11
12 #include <common.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/prcm.h>
16 #include <asm/arch/sys_proto.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19
20 #ifdef CONFIG_SPL_BUILD
clock_init_safe(void)21 void clock_init_safe(void)
22 {
23 struct sunxi_ccm_reg * const ccm =
24 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
25
26 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
27 struct sunxi_prcm_reg * const prcm =
28 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
29
30 /* Set PLL ldo voltage without this PLL6 does not work properly */
31 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
32 PRCM_PLL_CTRL_LDO_KEY);
33 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
34 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
35 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
36 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
37 #endif
38
39 #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
40 /* Set PLL lock enable bits and switch to old lock mode */
41 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
42 #endif
43
44 clock_set_pll1(408000000);
45
46 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
47 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
48 ;
49
50 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
51
52 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
53 if (IS_ENABLED(CONFIG_MACH_SUN6I))
54 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
55
56 #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
57 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
58 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);
59 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
60 setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
61 #endif
62 }
63 #endif
64
clock_init_sec(void)65 void clock_init_sec(void)
66 {
67 #ifdef CONFIG_MACH_SUNXI_H3_H5
68 struct sunxi_ccm_reg * const ccm =
69 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
70 struct sunxi_prcm_reg * const prcm =
71 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
72
73 setbits_le32(&ccm->ccu_sec_switch,
74 CCM_SEC_SWITCH_MBUS_NONSEC |
75 CCM_SEC_SWITCH_BUS_NONSEC |
76 CCM_SEC_SWITCH_PLL_NONSEC);
77 setbits_le32(&prcm->prcm_sec_switch,
78 PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
79 PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
80 PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
81 #endif
82 }
83
clock_init_uart(void)84 void clock_init_uart(void)
85 {
86 #if CONFIG_CONS_INDEX < 5
87 struct sunxi_ccm_reg *const ccm =
88 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
89
90 /* uart clock source is apb2 */
91 writel(APB2_CLK_SRC_OSC24M|
92 APB2_CLK_RATE_N_1|
93 APB2_CLK_RATE_M(1),
94 &ccm->apb2_div);
95
96 /* open the clock for uart */
97 setbits_le32(&ccm->apb2_gate,
98 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
99 CONFIG_CONS_INDEX - 1));
100
101 /* deassert uart reset */
102 setbits_le32(&ccm->apb2_reset_cfg,
103 1 << (APB2_RESET_UART_SHIFT +
104 CONFIG_CONS_INDEX - 1));
105 #else
106 /* enable R_PIO and R_UART clocks, and de-assert resets */
107 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
108 #endif
109 }
110
111 #ifdef CONFIG_SPL_BUILD
clock_set_pll1(unsigned int clk)112 void clock_set_pll1(unsigned int clk)
113 {
114 struct sunxi_ccm_reg * const ccm =
115 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
116 const int p = 0;
117 int k = 1;
118 int m = 1;
119
120 if (clk > 1152000000) {
121 k = 2;
122 } else if (clk > 768000000) {
123 k = 4;
124 m = 2;
125 }
126
127 /* Switch to 24MHz clock while changing PLL1 */
128 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
129 ATB_DIV_2 << ATB_DIV_SHIFT |
130 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
131 &ccm->cpu_axi_cfg);
132
133 /*
134 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
135 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
136 */
137 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
138 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
139 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
140 sdelay(200);
141
142 /* Switch CPU to PLL1 */
143 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
144 ATB_DIV_2 << ATB_DIV_SHIFT |
145 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
146 &ccm->cpu_axi_cfg);
147 }
148 #endif
149
clock_set_pll3(unsigned int clk)150 void clock_set_pll3(unsigned int clk)
151 {
152 struct sunxi_ccm_reg * const ccm =
153 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
154 #ifdef CONFIG_SUNXI_DE2
155 const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
156 #else
157 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
158 #endif
159
160 if (clk == 0) {
161 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
162 return;
163 }
164
165 /* PLL3 rate = 24000000 * n / m */
166 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
167 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
168 &ccm->pll3_cfg);
169 }
170
171 #ifdef CONFIG_SUNXI_DE2
clock_set_pll3_factors(int m,int n)172 void clock_set_pll3_factors(int m, int n)
173 {
174 struct sunxi_ccm_reg * const ccm =
175 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
176
177 /* PLL3 rate = 24000000 * n / m */
178 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
179 CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
180 &ccm->pll3_cfg);
181
182 while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
183 ;
184 }
185 #endif
186
clock_set_pll5(unsigned int clk,bool sigma_delta_enable)187 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
188 {
189 struct sunxi_ccm_reg * const ccm =
190 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
191 const int max_n = 32;
192 int k = 1, m = 2;
193
194 #ifdef CONFIG_MACH_SUNXI_H3_H5
195 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
196 CCM_PLL5_TUN_INIT_FREQ_MASK,
197 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
198 #endif
199
200 if (sigma_delta_enable)
201 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
202
203 /* PLL5 rate = 24000000 * n * k / m */
204 if (clk > 24000000 * k * max_n / m) {
205 m = 1;
206 if (clk > 24000000 * k * max_n / m)
207 k = 2;
208 }
209 writel(CCM_PLL5_CTRL_EN |
210 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
211 CCM_PLL5_CTRL_UPD |
212 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
213 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
214
215 udelay(5500);
216 }
217
218 #ifdef CONFIG_MACH_SUN6I
clock_set_mipi_pll(unsigned int clk)219 void clock_set_mipi_pll(unsigned int clk)
220 {
221 struct sunxi_ccm_reg * const ccm =
222 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
223 unsigned int k, m, n, value, diff;
224 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
225 unsigned int src = clock_get_pll3();
226
227 /* All calculations are in KHz to avoid overflows */
228 clk /= 1000;
229 src /= 1000;
230
231 /* Pick the closest lower clock */
232 for (k = 1; k <= 4; k++) {
233 for (m = 1; m <= 16; m++) {
234 for (n = 1; n <= 16; n++) {
235 value = src * n * k / m;
236 if (value > clk)
237 continue;
238
239 diff = clk - value;
240 if (diff < best_diff) {
241 best_diff = diff;
242 best_k = k;
243 best_m = m;
244 best_n = n;
245 }
246 if (diff == 0)
247 goto done;
248 }
249 }
250 }
251
252 done:
253 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
254 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
255 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
256 }
257 #endif
258
259 #ifdef CONFIG_SUNXI_DE2
clock_set_pll10(unsigned int clk)260 void clock_set_pll10(unsigned int clk)
261 {
262 struct sunxi_ccm_reg * const ccm =
263 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
264 const int m = 2; /* 12 MHz steps */
265
266 if (clk == 0) {
267 clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
268 return;
269 }
270
271 /* PLL10 rate = 24000000 * n / m */
272 writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
273 CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
274 &ccm->pll10_cfg);
275
276 while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
277 ;
278 }
279 #endif
280
281 #if defined(CONFIG_MACH_SUN8I_A33) || \
282 defined(CONFIG_MACH_SUN8I_R40) || \
283 defined(CONFIG_MACH_SUN50I)
clock_set_pll11(unsigned int clk,bool sigma_delta_enable)284 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
285 {
286 struct sunxi_ccm_reg * const ccm =
287 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
288
289 if (sigma_delta_enable)
290 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
291
292 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
293 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
294 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
295
296 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
297 ;
298 }
299 #endif
300
clock_get_pll3(void)301 unsigned int clock_get_pll3(void)
302 {
303 struct sunxi_ccm_reg *const ccm =
304 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
305 uint32_t rval = readl(&ccm->pll3_cfg);
306 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
307 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
308
309 /* Multiply by 1000 after dividing by m to avoid integer overflows */
310 return (24000 * n / m) * 1000;
311 }
312
clock_get_pll6(void)313 unsigned int clock_get_pll6(void)
314 {
315 struct sunxi_ccm_reg *const ccm =
316 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
317 uint32_t rval = readl(&ccm->pll6_cfg);
318 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
319 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
320 return 24000000 * n * k / 2;
321 }
322
clock_get_mipi_pll(void)323 unsigned int clock_get_mipi_pll(void)
324 {
325 struct sunxi_ccm_reg *const ccm =
326 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
327 uint32_t rval = readl(&ccm->mipi_pll_cfg);
328 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
329 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
330 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
331 unsigned int src = clock_get_pll3();
332
333 /* Multiply by 1000 after dividing by m to avoid integer overflows */
334 return ((src / 1000) * n * k / m) * 1000;
335 }
336
clock_set_de_mod_clock(u32 * clk_cfg,unsigned int hz)337 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
338 {
339 int pll = clock_get_pll6() * 2;
340 int div = 1;
341
342 while ((pll / div) > hz)
343 div++;
344
345 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
346 clk_cfg);
347 }
348