1 #include <common.h>
2 #include <asm/arch/dram.h>
3 #include <asm/arch/cpu.h>
4
mctl_set_timing_params(uint16_t socid,struct dram_para * para)5 void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
6 {
7 struct sunxi_mctl_ctl_reg * const mctl_ctl =
8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
9
10 u8 tccd = 2;
11 u8 tfaw = ns_to_t(50);
12 u8 trrd = max(ns_to_t(10), 4);
13 u8 trcd = ns_to_t(15);
14 u8 trc = ns_to_t(53);
15 u8 txp = max(ns_to_t(8), 3);
16 u8 twtr = max(ns_to_t(8), 4);
17 u8 trtp = max(ns_to_t(8), 4);
18 u8 twr = max(ns_to_t(15), 3);
19 u8 trp = ns_to_t(15);
20 u8 tras = ns_to_t(38);
21 u16 trefi = ns_to_t(7800) / 32;
22 u16 trfc = ns_to_t(350);
23
24 u8 tmrw = 0;
25 u8 tmrd = 4;
26 u8 tmod = 12;
27 u8 tcke = 3;
28 u8 tcksrx = 5;
29 u8 tcksre = 5;
30 u8 tckesr = 4;
31 u8 trasmax = 24;
32
33 u8 tcl = 6; /* CL 12 */
34 u8 tcwl = 4; /* CWL 8 */
35 u8 t_rdata_en = 4;
36 u8 wr_latency = 2;
37
38 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
39 u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
40 u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
41 u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
42
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
46
47 /* set mode register */
48 writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
49 writel(0x40, &mctl_ctl->mr[1]);
50 writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
51 writel(0x0, &mctl_ctl->mr[3]);
52
53 if (socid == SOCID_R40)
54 writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */
55
56 /* set DRAM timing */
57 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
58 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
59 &mctl_ctl->dramtmg[0]);
60 writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
61 &mctl_ctl->dramtmg[1]);
62 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
63 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
64 &mctl_ctl->dramtmg[2]);
65 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
66 &mctl_ctl->dramtmg[3]);
67 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
68 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
69 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
71 &mctl_ctl->dramtmg[5]);
72
73 /* set two rank timing */
74 clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
75 ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
76
77 /* set PHY interface timing, write latency and read latency configure */
78 writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
79 (wr_latency << 0), &mctl_ctl->pitmg[0]);
80
81 /* set PHY timing, PTR0-2 use default */
82 writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
83 writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
84
85 /* set refresh timing */
86 writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
87 }
88