1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
4  * Michal Simek <michal.simek@xilinx.com>
5  * (This file derived from arch/arm/mach-zynqmp/cpu.c)
6  *
7  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
8  */
9 
10 #include <common.h>
11 #include <asm/system.h>
12 #include <asm/armv8/mmu.h>
13 
14 /* size: IO + NR_DRAM_BANKS + terminator */
15 struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
16 	{
17 		.virt = 0x0UL,
18 		.phys = 0x0UL,
19 		.size = 0x80000000UL,
20 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
21 			 PTE_BLOCK_NON_SHARE |
22 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
23 	}, {
24 		.virt = 0x80000000UL,
25 		.phys = 0x80000000UL,
26 		.size = 0x80000000UL,
27 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
28 			 PTE_BLOCK_INNER_SHARE
29 	}, {
30 		/* List terminator */
31 		0,
32 	}
33 };
34 
35 struct mm_region *mem_map = tegra_mem_map;
36