1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 /* Tegra cache routines */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch-tegra/ap.h>
11 #if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL)
12 #include <asm/arch/gp_padctrl.h>
13 #endif
14
15 #ifndef CONFIG_ARM64
config_cache(void)16 void config_cache(void)
17 {
18 u32 reg = 0;
19
20 /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
21 asm volatile(
22 "mrc p15, 0, r0, c1, c0, 1\n"
23 "orr r0, r0, #0x41\n"
24 "mcr p15, 0, r0, c1, c0, 1\n");
25
26 /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
27 if (tegra_get_chip() < CHIPID_TEGRA114)
28 return;
29
30 /*
31 * Systems with an architectural L2 cache must not use the PL310.
32 * Config L2CTLR here for a data RAM latency of 3 cycles.
33 */
34 asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
35 reg &= ~7;
36 reg |= 2;
37 asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
38 }
39 #endif
40