1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2012
4  * NVIDIA Inc, <www.nvidia.com>
5  *
6  * Allen Martin <amartin@nvidia.com>
7  */
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <log.h>
11 #include <spl.h>
12 
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/pinmux.h>
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/apb_misc.h>
18 #include <asm/arch-tegra/board.h>
19 #include <asm/spl.h>
20 #include "cpu.h"
21 
spl_board_init(void)22 void spl_board_init(void)
23 {
24 	struct apb_misc_pp_ctlr *apb_misc =
25 				(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
26 
27 	/* enable JTAG */
28 	writel(0xC0, &apb_misc->cfg_ctl);
29 
30 	board_init_uart_f();
31 
32 	/* Initialize periph GPIOs */
33 	gpio_early_init_uart();
34 
35 	clock_early_init();
36 #ifdef CONFIG_DEBUG_UART
37 	debug_uart_init();
38 #endif
39 	preloader_console_init();
40 }
41 
spl_boot_device(void)42 u32 spl_boot_device(void)
43 {
44 	return BOOT_DEVICE_RAM;
45 }
46 
jump_to_image_no_args(struct spl_image_info * spl_image)47 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
48 {
49 	debug("image entry point: 0x%lX\n", spl_image->entry_point);
50 
51 	start_cpu((u32)spl_image->entry_point);
52 	halt_avp();
53 }
54