1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
7
8 #include <common.h>
9 #include <errno.h>
10 #include <log.h>
11 #include <asm/global_data.h>
12 #include <dm/of_access.h>
13 #include <dm/ofnode.h>
14 #include <linux/delay.h>
15
16 #include "../xusb-padctl-common.h"
17
18 #include <asm/arch/clock.h>
19
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 enum tegra210_function {
25 TEGRA210_FUNC_SNPS,
26 TEGRA210_FUNC_XUSB,
27 TEGRA210_FUNC_UART,
28 TEGRA210_FUNC_PCIE_X1,
29 TEGRA210_FUNC_PCIE_X4,
30 TEGRA210_FUNC_USB3,
31 TEGRA210_FUNC_SATA,
32 TEGRA210_FUNC_RSVD,
33 };
34
35 static const char *const tegra210_functions[] = {
36 "snps",
37 "xusb",
38 "uart",
39 "pcie-x1",
40 "pcie-x4",
41 "usb3",
42 "sata",
43 "rsvd",
44 };
45
46 static const unsigned int tegra210_otg_functions[] = {
47 TEGRA210_FUNC_SNPS,
48 TEGRA210_FUNC_XUSB,
49 TEGRA210_FUNC_UART,
50 TEGRA210_FUNC_RSVD,
51 };
52
53 static const unsigned int tegra210_usb_functions[] = {
54 TEGRA210_FUNC_SNPS,
55 TEGRA210_FUNC_XUSB,
56 };
57
58 static const unsigned int tegra210_pci_functions[] = {
59 TEGRA210_FUNC_PCIE_X1,
60 TEGRA210_FUNC_USB3,
61 TEGRA210_FUNC_SATA,
62 TEGRA210_FUNC_PCIE_X4,
63 };
64
65 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
66 { \
67 .name = _name, \
68 .offset = _offset, \
69 .shift = _shift, \
70 .mask = _mask, \
71 .iddq = _iddq, \
72 .num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \
73 .funcs = tegra210_##_funcs##_functions, \
74 }
75
76 static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
77 TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
78 TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
79 TEGRA210_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
80 TEGRA210_LANE("otg-3", 0x004, 6, 0x3, 0, otg),
81 TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
82 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
83 TEGRA210_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
84 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, 1, pci),
85 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, 2, pci),
86 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, 3, pci),
87 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, 4, pci),
88 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, 5, pci),
89 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, 6, pci),
90 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, 7, pci),
91 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, 8, pci),
92 };
93
94 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
95 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
96 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
97 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
98
tegra_xusb_padctl_enable(struct tegra_xusb_padctl * padctl)99 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
100 {
101 u32 value;
102
103 if (padctl->enable++ > 0)
104 return 0;
105
106 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
107 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
108 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
109
110 udelay(100);
111
112 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
113 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
114 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
115
116 udelay(100);
117
118 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
119 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
120 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
121
122 return 0;
123 }
124
tegra_xusb_padctl_disable(struct tegra_xusb_padctl * padctl)125 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
126 {
127 u32 value;
128
129 if (padctl->enable == 0) {
130 pr_err("unbalanced enable/disable");
131 return 0;
132 }
133
134 if (--padctl->enable > 0)
135 return 0;
136
137 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
138 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
139 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
140
141 udelay(100);
142
143 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
144 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
145 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
146
147 udelay(100);
148
149 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
150 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
151 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
152
153 return 0;
154 }
155
phy_prepare(struct tegra_xusb_phy * phy)156 static int phy_prepare(struct tegra_xusb_phy *phy)
157 {
158 int err;
159
160 err = tegra_xusb_padctl_enable(phy->padctl);
161 if (err < 0)
162 return err;
163
164 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
165
166 return 0;
167 }
168
phy_unprepare(struct tegra_xusb_phy * phy)169 static int phy_unprepare(struct tegra_xusb_phy *phy)
170 {
171 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
172
173 return tegra_xusb_padctl_disable(phy->padctl);
174 }
175
176 #define XUSB_PADCTL_USB3_PAD_MUX 0x28
177 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
178 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
179 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
180 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
181 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
182 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
183 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
184 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
185 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
186
187 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
188 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
189 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
190 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
191 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
192 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
193 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
194 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
195 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
196 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
197
198 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
199 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
200 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
201 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
202 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
203 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
204
205 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
206 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
207 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
208 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
209 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
210 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
211
212 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
213 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
214 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
215
216 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
217 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
218 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
219 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
220 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
221
222 #define CLK_RST_XUSBIO_PLL_CFG0 0x51c
223 #define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
224 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
225 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
226 #define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
227 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
228
pcie_phy_enable(struct tegra_xusb_phy * phy)229 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
230 {
231 struct tegra_xusb_padctl *padctl = phy->padctl;
232 unsigned long start;
233 u32 value;
234
235 debug("> %s(phy=%p)\n", __func__, phy);
236
237 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
238 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
239 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
240 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
241
242 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
243 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
244 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
245 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
246
247 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
248 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
249 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
250
251 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
252 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
253 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
254
255 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
256 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
257 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
258
259 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
260 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
261 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
262 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
263 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
264 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
265
266 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
267 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
268 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
269 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
270 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
271
272 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
273 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
274 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
275
276 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
277 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
278 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
279
280 udelay(1);
281
282 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
283 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
284 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
285
286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
287 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
288 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
289
290 debug(" waiting for calibration\n");
291
292 start = get_timer(0);
293
294 while (get_timer(start) < 250) {
295 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
296 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
297 break;
298 }
299 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
300 debug(" timeout\n");
301 return -ETIMEDOUT;
302 }
303 debug(" done\n");
304
305 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
306 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
307 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
308
309 debug(" waiting for calibration to stop\n");
310
311 start = get_timer(0);
312
313 while (get_timer(start) < 250) {
314 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
315 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
316 break;
317 }
318 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
319 debug(" timeout\n");
320 return -ETIMEDOUT;
321 }
322 debug(" done\n");
323
324 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
325 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
326 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
327
328 debug(" waiting for PLL to lock...\n");
329 start = get_timer(0);
330
331 while (get_timer(start) < 250) {
332 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
333 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
334 break;
335 }
336 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
337 debug(" timeout\n");
338 return -ETIMEDOUT;
339 }
340 debug(" done\n");
341
342 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
343 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
344 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
345 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
346
347 debug(" waiting for register calibration...\n");
348 start = get_timer(0);
349
350 while (get_timer(start) < 250) {
351 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
352 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
353 break;
354 }
355 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
356 debug(" timeout\n");
357 return -ETIMEDOUT;
358 }
359 debug(" done\n");
360
361 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
362 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
363 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
364
365 debug(" waiting for register calibration to stop...\n");
366 start = get_timer(0);
367
368 while (get_timer(start) < 250) {
369 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
370 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
371 break;
372 }
373 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
374 debug(" timeout\n");
375 return -ETIMEDOUT;
376 }
377 debug(" done\n");
378
379 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
380 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
381 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
382
383 debug("< %s()\n", __func__);
384 return 0;
385 }
386
pcie_phy_disable(struct tegra_xusb_phy * phy)387 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
388 {
389 return 0;
390 }
391
392 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
393 .prepare = phy_prepare,
394 .enable = pcie_phy_enable,
395 .disable = pcie_phy_disable,
396 .unprepare = phy_unprepare,
397 };
398
399 static struct tegra_xusb_phy tegra210_phys[] = {
400 {
401 .type = TEGRA_XUSB_PADCTL_PCIE,
402 .ops = &pcie_phy_ops,
403 .padctl = &padctl,
404 },
405 };
406
407 static const struct tegra_xusb_padctl_soc tegra210_socdata = {
408 .lanes = tegra210_lanes,
409 .num_lanes = ARRAY_SIZE(tegra210_lanes),
410 .functions = tegra210_functions,
411 .num_functions = ARRAY_SIZE(tegra210_functions),
412 .phys = tegra210_phys,
413 .num_phys = ARRAY_SIZE(tegra210_phys),
414 };
415
tegra_xusb_padctl_init(void)416 void tegra_xusb_padctl_init(void)
417 {
418 ofnode nodes[1];
419 int count = 0;
420 int ret;
421
422 debug("%s: start\n", __func__);
423 if (of_live_active()) {
424 struct device_node *np = of_find_compatible_node(NULL, NULL,
425 "nvidia,tegra210-xusb-padctl");
426
427 debug("np=%p\n", np);
428 if (np) {
429 nodes[0] = np_to_ofnode(np);
430 count = 1;
431 }
432 } else {
433 int node_offsets[1];
434 int i;
435
436 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
437 COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
438 node_offsets, ARRAY_SIZE(node_offsets));
439 for (i = 0; i < count; i++)
440 nodes[i] = offset_to_ofnode(node_offsets[i]);
441 }
442
443 ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
444 debug("%s: done, ret=%d\n", __func__, ret);
445 }
446
tegra_xusb_padctl_exit(void)447 void tegra_xusb_padctl_exit(void)
448 {
449 u32 value;
450
451 debug("> %s\n", __func__);
452
453 value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
454 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
455 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
456 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
457 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
458 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
459 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
460 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
461 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
462 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
463 padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
464
465 value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
466 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
467 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
468 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
469 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
470 padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
471
472 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
473 while (padctl.enable)
474 tegra_xusb_padctl_disable(&padctl);
475
476 debug("< %s()\n", __func__);
477 }
478