1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <common.h>
7 #include <log.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/flow.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/tegra_i2c.h>
15 #include <linux/delay.h>
16 #include "../cpu.h"
17
18 /* Tegra30-specific CPU init code */
tegra_i2c_ll_write_addr(uint addr,uint config)19 void tegra_i2c_ll_write_addr(uint addr, uint config)
20 {
21 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
22
23 writel(addr, ®->cmd_addr0);
24 writel(config, ®->cnfg);
25 }
26
tegra_i2c_ll_write_data(uint data,uint config)27 void tegra_i2c_ll_write_data(uint data, uint config)
28 {
29 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
30
31 writel(data, ®->cmd_data1);
32 writel(config, ®->cnfg);
33 }
34
35 #define TPS62366A_I2C_ADDR 0xC0
36 #define TPS62366A_SET1_REG 0x01
37 #define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
38
39 #define TPS62361B_I2C_ADDR 0xC0
40 #define TPS62361B_SET3_REG 0x03
41 #define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
42
43 #define TPS65911_I2C_ADDR 0x5A
44 #define TPS65911_VDDCTRL_OP_REG 0x28
45 #define TPS65911_VDDCTRL_SR_REG 0x27
46 #define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
47 #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
48 #define I2C_SEND_2_BYTES 0x0A02
49
enable_cpu_power_rail(void)50 static void enable_cpu_power_rail(void)
51 {
52 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
53 u32 reg;
54
55 debug("enable_cpu_power_rail entry\n");
56 reg = readl(&pmc->pmc_cntrl);
57 reg |= CPUPWRREQ_OE;
58 writel(reg, &pmc->pmc_cntrl);
59
60 /* Set VDD_CORE to 1.200V. */
61 #ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
62 tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
63 tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
64 #endif
65 #ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
66 tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
67 tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
68 #endif
69 udelay(1000);
70
71 /*
72 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
73 * First set VDD to 1.0125V, then enable the VDD regulator.
74 */
75 tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
76 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
77 udelay(1000);
78 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
79 udelay(10 * 1000);
80 }
81
82 /**
83 * The T30 requires some special clock initialization, including setting up
84 * the dvc i2c, turning on mselect and selecting the G CPU cluster
85 */
t30_init_clocks(void)86 void t30_init_clocks(void)
87 {
88 struct clk_rst_ctlr *clkrst =
89 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
90 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
91 u32 val;
92
93 debug("t30_init_clocks entry\n");
94 /* Set active CPU cluster to G */
95 clrbits_le32(flow->cluster_control, 1 << 0);
96
97 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
98
99 val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
100 (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
101 (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
102 (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
103 writel(val, &clkrst->crc_clk_sys_rate);
104
105 /* Put i2c, mselect in reset and enable clocks */
106 reset_set_enable(PERIPH_ID_DVC_I2C, 1);
107 clock_set_enable(PERIPH_ID_DVC_I2C, 1);
108 reset_set_enable(PERIPH_ID_MSELECT, 1);
109 clock_set_enable(PERIPH_ID_MSELECT, 1);
110
111 /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
112 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
113
114 /*
115 * Our high-level clock routines are not available prior to
116 * relocation. We use the low-level functions which require a
117 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
118 */
119 clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
120
121 /*
122 * Give clocks time to stabilize, then take i2c and mselect out of
123 * reset
124 */
125 udelay(1000);
126 reset_set_enable(PERIPH_ID_DVC_I2C, 0);
127 reset_set_enable(PERIPH_ID_MSELECT, 0);
128 }
129
set_cpu_running(int run)130 static void set_cpu_running(int run)
131 {
132 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
133
134 debug("set_cpu_running entry, run = %d\n", run);
135 writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
136 }
137
start_cpu(u32 reset_vector)138 void start_cpu(u32 reset_vector)
139 {
140 debug("start_cpu entry, reset_vector = %x\n", reset_vector);
141 t30_init_clocks();
142
143 /* Enable VDD_CPU */
144 enable_cpu_power_rail();
145
146 set_cpu_running(0);
147
148 /* Hold the CPUs in reset */
149 reset_A9_cpu(1);
150
151 /* Disable the CPU clock */
152 enable_cpu_clock(0);
153
154 /* Enable CoreSight */
155 clock_enable_coresight(1);
156
157 /*
158 * Set the entry point for CPU execution from reset,
159 * if it's a non-zero value.
160 */
161 if (reset_vector)
162 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
163
164 /* Enable the CPU clock */
165 enable_cpu_clock(1);
166
167 /* If the CPU doesn't already have power, power it up */
168 powerup_cpu();
169
170 /* Take the CPU out of reset */
171 reset_A9_cpu(0);
172
173 set_cpu_running(1);
174 }
175