1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
12 #include <linux/io.h>
13 #include <linux/sizes.h>
14
15 #include "../sc64-regs.h"
16 #include "pll.h"
17
18 /* PLL type: SSC */
19 #define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
20 #define SC_PLLCTRL_SSC_EN BIT(31)
21 #define SC_PLLCTRL2_NRSTDS BIT(28)
22 #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
23 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
24
25 /* PLL type: VPLL27 */
26 #define SC_VPLL27CTRL_WP BIT(0)
27 #define SC_VPLL27CTRL3_K_LD BIT(28)
28
29 /* PLL type: DSPLL */
30 #define SC_DSPLLCTRL2_K_LD BIT(28)
31
uniphier_ld20_sscpll_init(unsigned long reg_base,unsigned int freq,unsigned int ssc_rate,unsigned int divn)32 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
33 unsigned int ssc_rate, unsigned int divn)
34 {
35 void __iomem *base = sc_base + reg_base;
36 u32 tmp;
37
38 if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
39 tmp = readl(base); /* SSCPLLCTRL */
40 tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
41 tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK,
42 DIV_ROUND_CLOSEST(487UL * freq * ssc_rate,
43 divn * 512));
44 writel(tmp, base);
45
46 tmp = readl(base + 4);
47 tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
48 tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK,
49 DIV_ROUND_CLOSEST(21431887UL * freq,
50 divn * 512));
51 writel(tmp, base + 4);
52
53 udelay(50);
54 }
55
56 tmp = readl(base + 4); /* SSCPLLCTRL2 */
57 tmp |= SC_PLLCTRL2_NRSTDS;
58 writel(tmp, base + 4);
59
60 return 0;
61 }
62
uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)63 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
64 {
65 void __iomem *base = sc_base + reg_base;
66 u32 tmp;
67
68 tmp = readl(base); /* SSCPLLCTRL */
69 tmp |= SC_PLLCTRL_SSC_EN;
70 writel(tmp, base);
71
72 return 0;
73 }
74
uniphier_ld20_sscpll_set_regi(unsigned long reg_base,unsigned regi)75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
76 {
77 void __iomem *base = sc_base + reg_base;
78 u32 tmp;
79
80 tmp = readl(base + 8); /* SSCPLLCTRL3 */
81 tmp &= ~SC_PLLCTRL3_REGI_MASK;
82 tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
83 writel(tmp, base + 8);
84
85 return 0;
86 }
87
uniphier_ld20_vpll27_init(unsigned long reg_base)88 int uniphier_ld20_vpll27_init(unsigned long reg_base)
89 {
90 void __iomem *base = sc_base + reg_base;
91 u32 tmp;
92
93 tmp = readl(base); /* VPLL27CTRL */
94 tmp |= SC_VPLL27CTRL_WP; /* write protect off */
95 writel(tmp, base);
96
97 tmp = readl(base + 8); /* VPLL27CTRL3 */
98 tmp |= SC_VPLL27CTRL3_K_LD;
99 writel(tmp, base + 8);
100
101 tmp = readl(base); /* VPLL27CTRL */
102 tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
103 writel(tmp, base);
104
105 return 0;
106 }
107
uniphier_ld20_dspll_init(unsigned long reg_base)108 int uniphier_ld20_dspll_init(unsigned long reg_base)
109 {
110 void __iomem *base = sc_base + reg_base;
111 u32 tmp;
112
113 tmp = readl(base + 4); /* DSPLLCTRL2 */
114 tmp |= SC_DSPLLCTRL2_K_LD;
115 writel(tmp, base + 4);
116
117 return 0;
118 }
119