1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
4 */
5
6 #include <debug_uart.h>
7 #include <linux/io.h>
8 #include <linux/serial_reg.h>
9
10 #include "../sg-regs.h"
11 #include "../soc-info.h"
12 #include "debug-uart.h"
13
14 #define UNIPHIER_UART_TX 0x00
15 #define UNIPHIER_UART_LCR_MCR 0x10
16 #define UNIPHIER_UART_LSR 0x14
17 #define UNIPHIER_UART_LDR 0x24
18
_debug_uart_putc(int c)19 static void _debug_uart_putc(int c)
20 {
21 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
22
23 while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
24 ;
25
26 writel(c, base + UNIPHIER_UART_TX);
27 }
28
29 #ifdef CONFIG_SPL_BUILD
sg_set_pinsel(unsigned int pin,unsigned int muxval,unsigned int mux_bits,unsigned int reg_stride)30 void sg_set_pinsel(unsigned int pin, unsigned int muxval,
31 unsigned int mux_bits, unsigned int reg_stride)
32 {
33 unsigned int shift = pin * mux_bits % 32;
34 void __iomem *reg = sg_base + SG_PINCTRL_BASE +
35 pin * mux_bits / 32 * reg_stride;
36 u32 mask = (1U << mux_bits) - 1;
37 u32 tmp;
38
39 tmp = readl(reg);
40 tmp &= ~(mask << shift);
41 tmp |= (mask & muxval) << shift;
42 writel(tmp, reg);
43 }
44
sg_set_iectrl(unsigned int pin)45 void sg_set_iectrl(unsigned int pin)
46 {
47 unsigned int bit = pin % 32;
48 void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4;
49 u32 tmp;
50
51 tmp = readl(reg);
52 tmp |= 1 << bit;
53 writel(tmp, reg);
54 }
55 #endif
56
_debug_uart_init(void)57 void _debug_uart_init(void)
58 {
59 #ifdef CONFIG_SPL_BUILD
60 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
61 unsigned int divisor;
62
63 switch (uniphier_get_soc_id()) {
64 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
65 case UNIPHIER_LD4_ID:
66 divisor = uniphier_ld4_debug_uart_init();
67 break;
68 #endif
69 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
70 case UNIPHIER_PRO4_ID:
71 divisor = uniphier_pro4_debug_uart_init();
72 break;
73 #endif
74 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
75 case UNIPHIER_SLD8_ID:
76 divisor = uniphier_sld8_debug_uart_init();
77 break;
78 #endif
79 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
80 case UNIPHIER_PRO5_ID:
81 divisor = uniphier_pro5_debug_uart_init();
82 break;
83 #endif
84 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
85 case UNIPHIER_PXS2_ID:
86 divisor = uniphier_pxs2_debug_uart_init();
87 break;
88 #endif
89 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
90 case UNIPHIER_LD6B_ID:
91 divisor = uniphier_ld6b_debug_uart_init();
92 break;
93 #endif
94 default:
95 return;
96 }
97
98 writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR);
99
100 writel(divisor, base + UNIPHIER_UART_LDR);
101 #endif
102 }
103 DEBUG_UART_FUNCS
104