1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
4  * Michal Simek <michal.simek@xilinx.com>
5  */
6 
7 #ifndef _ASM_ARCH_SYS_PROTO_H
8 #define _ASM_ARCH_SYS_PROTO_H
9 
10 #define ZYNQMP_CSU_SILICON_VER_MASK	0xF
11 #define KEY_PTR_LEN	32
12 #define IV_SIZE		12
13 #define RSA_KEY_SIZE	512
14 #define MODULUS_LEN	512
15 #define PRIV_EXPO_LEN	512
16 #define PUB_EXPO_LEN	4
17 
18 #define ZYNQMP_SHA3_INIT	1
19 #define ZYNQMP_SHA3_UPDATE	2
20 #define ZYNQMP_SHA3_FINAL	4
21 #define ZYNQMP_SHA3_SIZE	48
22 
23 #define ZYNQMP_FPGA_BIT_AUTH_DDR	1
24 #define ZYNQMP_FPGA_BIT_AUTH_OCM	2
25 #define ZYNQMP_FPGA_BIT_ENC_USR_KEY	3
26 #define ZYNQMP_FPGA_BIT_ENC_DEV_KEY	4
27 #define ZYNQMP_FPGA_BIT_NS		5
28 
29 #define ZYNQMP_FPGA_AUTH_DDR	1
30 
31 enum {
32 	IDCODE,
33 	VERSION,
34 	IDCODE2,
35 };
36 
37 enum {
38 	ZYNQMP_SILICON_V1,
39 	ZYNQMP_SILICON_V2,
40 	ZYNQMP_SILICON_V3,
41 	ZYNQMP_SILICON_V4,
42 };
43 
44 enum {
45 	TCM_LOCK,
46 	TCM_SPLIT,
47 };
48 
49 struct zynqmp_ipi_msg {
50 	size_t len;
51 	u32 *buf;
52 };
53 
54 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
55 unsigned int zynqmp_get_silicon_version(void);
56 
57 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
58 int zynqmp_mmio_read(const u32 address, u32 *value);
59 
60 void initialize_tcm(bool mode);
61 void mem_map_fill(void);
62 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
63 void tcm_init(u8 mode);
64 #endif
65 
66 #endif /* _ASM_ARCH_SYS_PROTO_H */
67