1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
4 *
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <init.h>
10 #include <watchdog.h>
11 #include <asm/immap.h>
12 #include <asm/io.h>
13
14 #if defined(CONFIG_M5307)
15 /*
16 * Simple mcf5307 chip select module init.
17 *
18 * Note: this chip has an issue reported in the device "errata":
19 * MCF5307ER Rev 4.2 reports @ section 35:
20 * Corrupted Return PC in Exception Stack Frame
21 * When processing an autovectored interrupt an error can occur that
22 * causes 0xFFFFFFFF to be written as the return PC value in the
23 * exception stack frame. The problem is caused by a conflict between
24 * an internal autovector access and a chip select mapped to the IACK
25 * address space (0xFFFFXXXX).
26 * Workaround:
27 * Set the C/I bit in the chip select mask register (CSMR) for the
28 * chip select that is mapped to 0xFFFFXXXX.
29 * This will prevent the chip select from asserting for IACK accesses.
30 */
31
32 #define MCF5307_SP_ERR_FIX(cs_base, mask) \
33 do { \
34 if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \
35 0xffff0000) \
36 setbits_be32(&mask, CSMR_CI); \
37 } while (0)
38
init_csm(void)39 void init_csm(void)
40 {
41 csm_t *csm = (csm_t *)(MMAP_CSM);
42
43 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
44 defined(CONFIG_SYS_CS0_CTRL))
45 out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
46 out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
47 out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
48 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
49 #else
50 #warning "Chip Select 0 are not initialized/used"
51 #endif
52 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
53 defined(CONFIG_SYS_CS1_CTRL))
54 out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
55 out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
56 out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
57 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
58 #endif
59 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
60 defined(CONFIG_SYS_CS2_CTRL))
61 out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
62 out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
63 out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
64 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
65 #endif
66 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
67 defined(CONFIG_SYS_CS3_CTRL))
68 out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
69 out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
70 out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
71 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
72 #endif
73 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
74 defined(CONFIG_SYS_CS4_CTRL))
75 out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
76 out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
77 out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
78 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
79 #endif
80 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
81 defined(CONFIG_SYS_CS5_CTRL))
82 out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
83 out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
84 out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
85 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
86 #endif
87 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
88 defined(CONFIG_SYS_CS6_CTRL))
89 out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
90 out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
91 out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
92 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
93 #endif
94 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
95 defined(CONFIG_SYS_CS7_CTRL))
96 out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
97 out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
98 out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
99 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
100 #endif
101 }
102
103 /*
104 * Set up the memory map and initialize registers
105 */
cpu_init_f(void)106 void cpu_init_f(void)
107 {
108 sim_t *sim = (sim_t *)(MMAP_SIM);
109
110 out_8(&sim->sypcr, 0x00);
111 out_8(&sim->swivr, 0x0f);
112 out_8(&sim->swsr, 0x00);
113 out_8(&sim->mpark, 0x00);
114
115 intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
116
117 /* timer 2 not masked */
118 out_be32(&icr->imr, 0xfffffbff);
119
120 out_8(&icr->icr0, 0x00); /* sw watchdog */
121 out_8(&icr->icr1, 0x00); /* timer 1 */
122 out_8(&icr->icr2, 0x88); /* timer 2 */
123 out_8(&icr->icr3, 0x00); /* i2c */
124 out_8(&icr->icr4, 0x00); /* uart 0 */
125 out_8(&icr->icr5, 0x00); /* uart 1 */
126 out_8(&icr->icr6, 0x00); /* dma 0 */
127 out_8(&icr->icr7, 0x00); /* dma 1 */
128 out_8(&icr->icr8, 0x00); /* dma 2 */
129 out_8(&icr->icr9, 0x00); /* dma 3 */
130
131 /* Chipselect Init */
132 init_csm();
133
134 /* enable data/instruction cache now */
135 icache_enable();
136 }
137
138 /*
139 * initialize higher level parts of CPU like timers
140 */
cpu_init_r(void)141 int cpu_init_r(void)
142 {
143 return 0;
144 }
145
uart_port_conf(int port)146 void uart_port_conf(int port)
147 {
148 }
149
arch_preboot_os(void)150 void arch_preboot_os(void)
151 {
152 /*
153 * OS can change interrupt offsets and are about to boot the OS so
154 * we need to make sure we disable all async interrupts.
155 */
156 intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
157
158 out_8(&icr->icr1, 0x00); /* timer 1 */
159 out_8(&icr->icr2, 0x00); /* timer 2 */
160 }
161 #endif
162