1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
4 */
5
6/ {
7	compatible = "fsl,mcf54x5";
8
9	aliases {
10		/* TO DO, clarify on serial, this SoC seems to have SPC and
11		 * no UARTS.
12		 */
13		spi0 = &dspi0;
14		fec0 = &fec0;
15		fec1 = &fec1;
16	};
17
18	soc {
19		compatible = "simple-bus";
20		#address-cells = <1>;
21		#size-cells = <1>;
22
23		mbar: mbar@80000000 {
24			compatible = "simple-bus";
25			#address-cells = <1>;
26			#size-cells = <1>;
27			ranges = <0x00000000 0x80000000 0x10000>;
28			reg = <0x80000000 0x10000>;
29
30			dspi0: dspi@8a00 {
31				compatible = "fsl,mcf-dspi";
32				#address-cells = <1>;
33				#size-cells = <0>;
34				reg = <0x8a00 0x100>;
35				spi-max-frequency = <50000000>;
36				num-cs = <4>;
37				spi-mode = <0>;
38				status = "disabled";
39			};
40
41			fec0: ethernet@9000 {
42				compatible = "fsl,mcf-dma-fec";
43				reg = <0x9000 0x800>;
44				mii-base = <0>;
45				max-speed = <100>;
46				timeout-loop = <50000>;
47				rx-task = <0>;
48				tx-task = <1>;
49				rx-piority = <6>;
50				tx-piority = <7>;
51				rx-init = <16>;
52				tx-init = <17>;
53				status = "disabled";
54			};
55
56			fec1: ethernet@9800 {
57				compatible = "fsl,mcf-dma-fec";
58				reg = <0x9800 0x800>;
59				mii-base = <1>;
60				max-speed = <100>;
61				timeout-loop = <50000>;
62				rx-task = <2>;
63				tx-task = <3>;
64				rx-piority = <6>;
65				tx-piority = <7>;
66				rx-init = <30>;
67				tx-init = <31>;
68				status = "disabled";
69			};
70		};
71	};
72};
73