1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * MCF5227x Internal Memory Map
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 #ifndef __DSPI_H__
10 #define __DSPI_H__
11 
12 /* DMA Serial Peripheral Interface (DSPI) */
13 typedef struct dspi {
14 	u32 mcr;	/* 0x00 */
15 	u32 resv0;	/* 0x04 */
16 	u32 tcr;	/* 0x08 */
17 	u32 ctar[8];	/* 0x0C - 0x28 */
18 	u32 sr;		/* 0x2C */
19 	u32 irsr;	/* 0x30 */
20 	u32 tfr;	/* 0x34 - PUSHR */
21 	u16 resv1;	/* 0x38 */
22 	u16 rfr;	/* 0x3A - POPR */
23 #ifdef CONFIG_MCF547x_8x
24 	u32 tfdr[4];	/* 0x3C */
25 	u8 resv2[0x30];	/* 0x40 */
26 	u32 rfdr[4];	/* 0x7C */
27 #else
28 	u32 tfdr[16];	/* 0x3C */
29 	u32 rfdr[16];	/* 0x7C */
30 #endif
31 } dspi_t;
32 
33 /* Module configuration */
34 #define DSPI_MCR_MSTR			(0x80000000)
35 #define DSPI_MCR_CSCK			(0x40000000)
36 #define DSPI_MCR_DCONF(x)		(((x)&0x03)<<28)
37 #define DSPI_MCR_FRZ			(0x08000000)
38 #define DSPI_MCR_MTFE			(0x04000000)
39 #define DSPI_MCR_PCSSE			(0x02000000)
40 #define DSPI_MCR_ROOE			(0x01000000)
41 #define DSPI_MCR_CSIS7			(0x00800000)
42 #define DSPI_MCR_CSIS6			(0x00400000)
43 #define DSPI_MCR_CSIS5			(0x00200000)
44 #define DSPI_MCR_CSIS4			(0x00100000)
45 #define DSPI_MCR_CSIS3			(0x00080000)
46 #define DSPI_MCR_CSIS2			(0x00040000)
47 #define DSPI_MCR_CSIS1			(0x00020000)
48 #define DSPI_MCR_CSIS0			(0x00010000)
49 #define DSPI_MCR_MDIS			(0x00004000)
50 #define DSPI_MCR_DTXF			(0x00002000)
51 #define DSPI_MCR_DRXF			(0x00001000)
52 #define DSPI_MCR_CTXF			(0x00000800)
53 #define DSPI_MCR_CRXF			(0x00000400)
54 #define DSPI_MCR_SMPL_PT(x)		(((x)&0x03)<<8)
55 #define DSPI_MCR_HALT			(0x00000001)
56 
57 /* Transfer count */
58 #define DSPI_TCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)
59 
60 /* Clock and transfer attributes */
61 #define DSPI_CTAR_DBR			(0x80000000)
62 #define DSPI_CTAR_TRSZ(x)		(((x)&0x0F)<<27)
63 #define DSPI_CTAR_CPOL			(0x04000000)
64 #define DSPI_CTAR_CPHA			(0x02000000)
65 #define DSPI_CTAR_LSBFE			(0x01000000)
66 #define DSPI_CTAR_PCSSCK(x)		(((x)&0x03)<<22)
67 #define DSPI_CTAR_PCSSCK_7CLK		(0x00A00000)
68 #define DSPI_CTAR_PCSSCK_5CLK		(0x00800000)
69 #define DSPI_CTAR_PCSSCK_3CLK		(0x00400000)
70 #define DSPI_CTAR_PCSSCK_1CLK		(0x00000000)
71 #define DSPI_CTAR_PASC(x)		(((x)&0x03)<<20)
72 #define DSPI_CTAR_PASC_7CLK		(0x00300000)
73 #define DSPI_CTAR_PASC_5CLK		(0x00200000)
74 #define DSPI_CTAR_PASC_3CLK		(0x00100000)
75 #define DSPI_CTAR_PASC_1CLK		(0x00000000)
76 #define DSPI_CTAR_PDT(x)		(((x)&0x03)<<18)
77 #define DSPI_CTAR_PDT_7CLK		(0x000A0000)
78 #define DSPI_CTAR_PDT_5CLK		(0x00080000)
79 #define DSPI_CTAR_PDT_3CLK		(0x00040000)
80 #define DSPI_CTAR_PDT_1CLK		(0x00000000)
81 #define DSPI_CTAR_PBR(x)		(((x)&0x03)<<16)
82 #define DSPI_CTAR_PBR_7CLK		(0x00030000)
83 #define DSPI_CTAR_PBR_5CLK		(0x00020000)
84 #define DSPI_CTAR_PBR_3CLK		(0x00010000)
85 #define DSPI_CTAR_PBR_1CLK		(0x00000000)
86 #define DSPI_CTAR_CSSCK(x)		(((x)&0x0F)<<12)
87 #define DSPI_CTAR_ASC(x)		(((x)&0x0F)<<8)
88 #define DSPI_CTAR_DT(x)			(((x)&0x0F)<<4)
89 #define DSPI_CTAR_BR(x)			(((x)&0x0F))
90 
91 /* Status */
92 #define DSPI_SR_TCF			(0x80000000)
93 #define DSPI_SR_TXRXS			(0x40000000)
94 #define DSPI_SR_EOQF			(0x10000000)
95 #define DSPI_SR_TFUF			(0x08000000)
96 #define DSPI_SR_TFFF			(0x02000000)
97 #define DSPI_SR_RFOF			(0x00080000)
98 #define DSPI_SR_RFDF			(0x00020000)
99 #define DSPI_SR_TXCTR(x)		(((x)&0x0F)<<12)
100 #define DSPI_SR_TXPTR(x)		(((x)&0x0F)<<8)
101 #define DSPI_SR_RXCTR(x)		(((x)&0x0F)<<4)
102 #define DSPI_SR_RXPTR(x)		(((x)&0x0F))
103 
104 /* DMA/interrupt request selct and enable */
105 #define DSPI_IRSR_TCFE			(0x80000000)
106 #define DSPI_IRSR_EOQFE			(0x10000000)
107 #define DSPI_IRSR_TFUFE			(0x08000000)
108 #define DSPI_IRSR_TFFFE			(0x02000000)
109 #define DSPI_IRSR_TFFFS			(0x01000000)
110 #define DSPI_IRSR_RFOFE			(0x00080000)
111 #define DSPI_IRSR_RFDFE			(0x00020000)
112 #define DSPI_IRSR_RFDFS			(0x00010000)
113 
114 /* Transfer control - 32-bit access */
115 #define DSPI_TFR_CONT			(0x80000000)
116 #define DSPI_TFR_CTAS(x)		(((x)&0x07)<<12)
117 #define DSPI_TFR_EOQ			(0x08000000)
118 #define DSPI_TFR_CTCNT			(0x04000000)
119 #define DSPI_TFR_CS7			(0x00800000)
120 #define DSPI_TFR_CS6			(0x00400000)
121 #define DSPI_TFR_CS5			(0x00200000)
122 #define DSPI_TFR_CS4			(0x00100000)
123 #define DSPI_TFR_CS3			(0x00080000)
124 #define DSPI_TFR_CS2			(0x00040000)
125 #define DSPI_TFR_CS1			(0x00020000)
126 #define DSPI_TFR_CS0			(0x00010000)
127 
128 /* Transfer Fifo */
129 #define DSPI_TFR_TXDATA(x)		(((x)&0xFFFF))
130 
131 /* Bit definitions and macros for DRFR */
132 #define DSPI_RFR_RXDATA(x)		(((x)&0xFFFF))
133 
134 /* Bit definitions and macros for DTFDR group */
135 #define DSPI_TFDR_TXDATA(x)		(((x)&0x0000FFFF))
136 #define DSPI_TFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)
137 
138 /* Bit definitions and macros for DRFDR group */
139 #define DSPI_RFDR_RXDATA(x)		(((x)&0x0000FFFF))
140 
141 /* Architecture-related operations */
142 void dspi_chip_select(int cs);
143 void dspi_chip_unselect(int cs);
144 
145 #endif				/* __DSPI_H__ */
146