1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 */
5
6#include <dt-bindings/clock/bcm6318-clock.h>
7#include <dt-bindings/dma/bcm6318-dma.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/power-domain/bcm6318-power-domain.h>
10#include <dt-bindings/reset/bcm6318-reset.h>
11#include "skeleton.dtsi"
12
13/ {
14	compatible = "brcm,bcm6318";
15
16	aliases {
17		spi0 = &spi;
18	};
19
20	cpus {
21		reg = <0x10000000 0x4>;
22		#address-cells = <1>;
23		#size-cells = <0>;
24		u-boot,dm-pre-reloc;
25
26		cpu@0 {
27			compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
28			device_type = "cpu";
29			reg = <0>;
30			u-boot,dm-pre-reloc;
31		};
32	};
33
34	clocks {
35		compatible = "simple-bus";
36		#address-cells = <1>;
37		#size-cells = <1>;
38		u-boot,dm-pre-reloc;
39
40		hsspi_pll: hsspi-pll {
41			compatible = "fixed-clock";
42			#clock-cells = <0>;
43			clock-frequency = <250000000>;
44		};
45
46		periph_osc: periph-osc {
47			compatible = "fixed-clock";
48			#clock-cells = <0>;
49			clock-frequency = <50000000>;
50			u-boot,dm-pre-reloc;
51		};
52
53		periph_clk: periph-clk {
54			compatible = "brcm,bcm6345-clk";
55			reg = <0x10000004 0x4>;
56			#clock-cells = <1>;
57		};
58
59		ubus_clk: ubus-clk {
60			compatible = "brcm,bcm6345-clk";
61			reg = <0x10000008 0x4>;
62			#clock-cells = <1>;
63		};
64	};
65
66	ubus {
67		compatible = "simple-bus";
68		#address-cells = <1>;
69		#size-cells = <1>;
70		u-boot,dm-pre-reloc;
71
72		periph_rst: reset-controller@10000010 {
73			compatible = "brcm,bcm6345-reset";
74			reg = <0x10000010 0x4>;
75			#reset-cells = <1>;
76		};
77
78		wdt: watchdog@10000068 {
79			compatible = "brcm,bcm6345-wdt";
80			reg = <0x10000068 0xc>;
81			clocks = <&periph_osc>;
82		};
83
84		wdt-reboot {
85			compatible = "wdt-reboot";
86			wdt = <&wdt>;
87		};
88
89		pll_cntl: syscon@10000074 {
90			compatible = "syscon";
91			reg = <0x10000074 0x4>;
92		};
93
94		syscon-reboot {
95			compatible = "syscon-reboot";
96			regmap = <&pll_cntl>;
97			offset = <0x0>;
98			mask = <0x1>;
99		};
100
101		gpio1: gpio-controller@10000080 {
102			compatible = "brcm,bcm6345-gpio";
103			reg = <0x10000080 0x4>, <0x10000088 0x4>;
104			gpio-controller;
105			#gpio-cells = <2>;
106			ngpios = <18>;
107
108			status = "disabled";
109		};
110
111		gpio0: gpio-controller@10000084 {
112			compatible = "brcm,bcm6345-gpio";
113			reg = <0x10000084 0x4>, <0x1000008c 0x4>;
114			gpio-controller;
115			#gpio-cells = <2>;
116
117			status = "disabled";
118		};
119
120		uart0: serial@10000100 {
121			compatible = "brcm,bcm6345-uart";
122			reg = <0x10000100 0x18>;
123			clocks = <&periph_osc>;
124
125			status = "disabled";
126		};
127
128		leds: led-controller@10000200 {
129			compatible = "brcm,bcm6328-leds";
130			reg = <0x10000200 0x28>;
131			#address-cells = <1>;
132			#size-cells = <0>;
133
134			status = "disabled";
135		};
136
137		periph_pwr: power-controller@100008e8 {
138			compatible = "brcm,bcm6328-power-domain";
139			reg = <0x100008e8 0x4>;
140			#power-domain-cells = <1>;
141		};
142
143		spi: spi@10003000 {
144			compatible = "brcm,bcm6328-hsspi";
145			#address-cells = <1>;
146			#size-cells = <0>;
147			reg = <0x10003000 0x600>;
148			clocks = <&periph_clk BCM6318_CLK_HSSPI>, <&hsspi_pll>;
149			clock-names = "hsspi", "pll";
150			resets = <&periph_rst BCM6318_RST_SPI>;
151			spi-max-frequency = <33333334>;
152			num-cs = <3>;
153
154			status = "disabled";
155		};
156
157		memory-controller@10004000 {
158			compatible = "brcm,bcm6318-mc";
159			reg = <0x10004000 0x38>;
160			u-boot,dm-pre-reloc;
161		};
162
163		ehci: usb-controller@10005000 {
164			compatible = "brcm,bcm6318-ehci", "generic-ehci";
165			reg = <0x10005000 0x100>;
166			phys = <&usbh>;
167			big-endian;
168
169			status = "disabled";
170		};
171
172		ohci: usb-controller@10005100 {
173			compatible = "brcm,bcm6318-ohci", "generic-ohci";
174			reg = <0x10005100 0x100>;
175			phys = <&usbh>;
176			big-endian;
177
178			status = "disabled";
179		};
180
181		usbh: usb-phy@10005200 {
182			compatible = "brcm,bcm6318-usbh";
183			reg = <0x10005200 0x30>;
184			#phy-cells = <0>;
185			clocks = <&periph_clk BCM6318_CLK_USB>;
186			clock-names = "usbh";
187			power-domains = <&periph_pwr BCM6318_PWR_USB>;
188			resets = <&periph_rst BCM6318_RST_USBH>;
189
190			status = "disabled";
191		};
192
193		enet: ethernet@10080000 {
194			compatible = "brcm,bcm6368-enet";
195			#address-cells = <1>;
196			#size-cells = <0>;
197			reg = <0x10080000 0x8000>;
198			clocks = <&periph_clk BCM6318_CLK_ROBOSW250>,
199				 <&periph_clk BCM6318_CLK_ROBOSW025>,
200				 <&ubus_clk BCM6318_UCLK_ROBOSW>;
201			resets = <&periph_rst BCM6318_RST_ENETSW>,
202				 <&periph_rst BCM6318_RST_EPHY>;
203			dmas = <&iudma BCM6318_DMA_ENETSW_RX>,
204			       <&iudma BCM6318_DMA_ENETSW_TX>;
205			dma-names = "rx",
206				    "tx";
207			brcm,num-ports = <5>;
208
209			status = "disabled";
210		};
211
212		iudma: dma-controller@10088000 {
213			compatible = "brcm,bcm6368-iudma";
214			reg = <0x10088000 0x80>,
215			      <0x10088200 0x80>,
216			      <0x10088400 0x80>;
217			reg-names = "dma",
218				    "dma-channels",
219				    "dma-sram";
220			#dma-cells = <1>;
221			dma-channels = <8>;
222		};
223	};
224};
225