1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 */
5
6#include <dt-bindings/clock/bcm63268-clock.h>
7#include <dt-bindings/dma/bcm63268-dma.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/power-domain/bcm63268-power-domain.h>
10#include <dt-bindings/reset/bcm63268-reset.h>
11#include "skeleton.dtsi"
12
13/ {
14	compatible = "brcm,bcm63268";
15
16	aliases {
17		spi0 = &lsspi;
18		spi1 = &hsspi;
19	};
20
21	cpus {
22		reg = <0x10000000 0x4>;
23		#address-cells = <1>;
24		#size-cells = <0>;
25		u-boot,dm-pre-reloc;
26
27		cpu@0 {
28			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
29			device_type = "cpu";
30			reg = <0>;
31			u-boot,dm-pre-reloc;
32		};
33
34		cpu@1 {
35			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
36			device_type = "cpu";
37			reg = <1>;
38			u-boot,dm-pre-reloc;
39		};
40	};
41
42	clocks {
43		compatible = "simple-bus";
44		#address-cells = <1>;
45		#size-cells = <1>;
46		u-boot,dm-pre-reloc;
47
48		hsspi_pll: hsspi-pll {
49			compatible = "fixed-clock";
50			#clock-cells = <0>;
51			clock-frequency = <400000000>;
52		};
53
54		periph_osc: periph-osc {
55			compatible = "fixed-clock";
56			#clock-cells = <0>;
57			clock-frequency = <50000000>;
58			u-boot,dm-pre-reloc;
59		};
60
61		periph_clk: periph-clk {
62			compatible = "brcm,bcm6345-clk";
63			reg = <0x10000004 0x4>;
64			#clock-cells = <1>;
65		};
66
67		timer_clk: timer-clk {
68			compatible = "brcm,bcm6345-clk";
69			reg = <0x100000ac 0x4>;
70			#clock-cells = <1>;
71		};
72	};
73
74	ubus {
75		compatible = "simple-bus";
76		#address-cells = <1>;
77		#size-cells = <1>;
78		u-boot,dm-pre-reloc;
79
80		pll_cntl: syscon@10000008 {
81			compatible = "syscon";
82			reg = <0x10000008 0x4>;
83		};
84
85		syscon-reboot {
86			compatible = "syscon-reboot";
87			regmap = <&pll_cntl>;
88			offset = <0x0>;
89			mask = <0x1>;
90		};
91
92		periph_rst: reset-controller@10000010 {
93			compatible = "brcm,bcm6345-reset";
94			reg = <0x10000010 0x4>;
95			#reset-cells = <1>;
96		};
97
98		wdt: watchdog@1000009c {
99			compatible = "brcm,bcm6345-wdt";
100			reg = <0x1000009c 0xc>;
101			clocks = <&periph_osc>;
102		};
103
104		wdt-reboot {
105			compatible = "wdt-reboot";
106			wdt = <&wdt>;
107		};
108
109		gpio1: gpio-controller@100000c0 {
110			compatible = "brcm,bcm6345-gpio";
111			reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
112			gpio-controller;
113			#gpio-cells = <2>;
114			ngpios = <20>;
115
116			status = "disabled";
117		};
118
119		gpio0: gpio-controller@100000c4 {
120			compatible = "brcm,bcm6345-gpio";
121			reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
122			gpio-controller;
123			#gpio-cells = <2>;
124
125			status = "disabled";
126		};
127
128		uart0: serial@10000180 {
129			compatible = "brcm,bcm6345-uart";
130			reg = <0x10000180 0x18>;
131			clocks = <&periph_osc>;
132
133			status = "disabled";
134		};
135
136		uart1: serial@100001a0 {
137			compatible = "brcm,bcm6345-uart";
138			reg = <0x100001a0 0x18>;
139			clocks = <&periph_osc>;
140
141			status = "disabled";
142		};
143
144		nand: nand-controller@10000200 {
145			#address-cells = <1>;
146			#size-cells = <0>;
147			compatible = "brcm,nand-bcm6368",
148				     "brcm,brcmnand-v4.0",
149				     "brcm,brcmnand";
150			reg-names = "nand",
151				    "nand-cache",
152				    "nand-int-base";
153			reg = <0x10000200 0x180>,
154			      <0x10000600 0x200>,
155			      <0x100000b0 0x10>;
156			clocks = <&periph_clk BCM63268_CLK_NAND>;
157			clock-names = "nand";
158
159			status = "disabled";
160		};
161
162		periph_pwr: power-controller@1000184c {
163			compatible = "brcm,bcm6328-power-domain";
164			reg = <0x1000184c 0x4>;
165			#power-domain-cells = <1>;
166		};
167
168		lsspi: spi@10000800 {
169			compatible = "brcm,bcm6358-spi";
170			reg = <0x10000800 0x70c>;
171			#address-cells = <1>;
172			#size-cells = <0>;
173			clocks = <&periph_clk BCM63268_CLK_SPI>;
174			resets = <&periph_rst BCM63268_RST_SPI>;
175			spi-max-frequency = <20000000>;
176			num-cs = <8>;
177
178			status = "disabled";
179		};
180
181		hsspi: spi@10001000 {
182			compatible = "brcm,bcm6328-hsspi";
183			#address-cells = <1>;
184			#size-cells = <0>;
185			reg = <0x10001000 0x600>;
186			clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
187			clock-names = "hsspi", "pll";
188			resets = <&periph_rst BCM63268_RST_SPI>;
189			spi-max-frequency = <50000000>;
190			num-cs = <8>;
191
192			status = "disabled";
193		};
194
195		leds: led-controller@10001900 {
196			compatible = "brcm,bcm6328-leds";
197			reg = <0x10001900 0x24>;
198			#address-cells = <1>;
199			#size-cells = <0>;
200
201			status = "disabled";
202		};
203
204		ehci: usb-controller@10002500 {
205			compatible = "brcm,bcm63268-ehci", "generic-ehci";
206			reg = <0x10002500 0x100>;
207			phys = <&usbh>;
208			big-endian;
209
210			status = "disabled";
211		};
212
213		ohci: usb-controller@10002600 {
214			compatible = "brcm,bcm63268-ohci", "generic-ohci";
215			reg = <0x10002600 0x100>;
216			phys = <&usbh>;
217			big-endian;
218
219			status = "disabled";
220		};
221
222		usbh: usb-phy@10002700 {
223			compatible = "brcm,bcm63268-usbh";
224			reg = <0x10002700 0x38>;
225			#phy-cells = <0>;
226			clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>;
227			clock-names = "usbh", "usb_ref";
228			power-domains = <&periph_pwr BCM63268_PWR_USBH>;
229			resets = <&periph_rst BCM63268_RST_USBH>;
230
231			status = "disabled";
232		};
233
234		memory-controller@10003000 {
235			compatible = "brcm,bcm6328-mc";
236			reg = <0x10003000 0x894>;
237			u-boot,dm-pre-reloc;
238		};
239
240		iudma: dma-controller@1000d800 {
241			compatible = "brcm,bcm6368-iudma";
242			reg = <0x1000d800 0x80>,
243			      <0x1000da00 0x80>,
244			      <0x1000dc00 0x80>;
245			reg-names = "dma",
246				    "dma-channels",
247				    "dma-sram";
248			#dma-cells = <1>;
249			dma-channels = <8>;
250		};
251
252		enet: ethernet@10700000 {
253			compatible = "brcm,bcm6368-enet";
254			#address-cells = <1>;
255			#size-cells = <0>;
256			reg = <0x10700000 0x10000>;
257			clocks = <&periph_clk BCM63268_CLK_GMAC>,
258				 <&periph_clk BCM63268_CLK_ROBOSW>,
259				 <&periph_clk BCM63268_CLK_ROBOSW250>,
260				 <&timer_clk BCM63268_TCLK_EPHY1>,
261				 <&timer_clk BCM63268_TCLK_EPHY2>,
262				 <&timer_clk BCM63268_TCLK_EPHY3>,
263				 <&timer_clk BCM63268_TCLK_GPHY>;
264			resets = <&periph_rst BCM63268_RST_ENETSW>,
265				 <&periph_rst BCM63268_RST_EPHY>,
266				 <&periph_rst BCM63268_RST_GPHY>;
267			dmas = <&iudma BCM63268_DMA_ENETSW_RX>,
268			       <&iudma BCM63268_DMA_ENETSW_TX>;
269			dma-names = "rx",
270				    "tx";
271			brcm,rgmii-override;
272			brcm,rgmii-timing;
273
274			status = "disabled";
275		};
276	};
277};
278