1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/dts-v1/;
7#include "mscc,luton.dtsi"
8#include <dt-bindings/mscc/luton_data.h>
9
10/ {
11	model = "Luton26 PCB090 Reference Board";
12	compatible = "mscc,luton-pcb090", "mscc,luton";
13
14	aliases {
15		serial0 = &uart0;
16		spi0 = &spi0;
17	};
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	gpio-leds {
24		compatible = "gpio-leds";
25
26		status_green {
27			label = "pcb090:green:status";
28			gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
29			default-state = "on";
30		};
31
32		status_red {
33			label = "pcb090:red:status";
34			gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
35			default-state = "off";
36		};
37	};
38};
39
40&sgpio {
41	status = "okay";
42	gpio-ranges = <&sgpio 0 0 96>;
43};
44
45&uart0 {
46	status = "okay";
47};
48
49&spi0 {
50	status = "okay";
51	spi-flash@0 {
52		compatible = "jedec,spi-nor";
53		spi-max-frequency = <18000000>; /* input clock */
54		reg = <0>; /* CS0 */
55		spi-cs-high;
56	};
57};
58
59&mdio0 {
60	status = "okay";
61
62	phy0: ethernet-phy@0 {
63		reg = <0>;
64	};
65	phy1: ethernet-phy@1 {
66		reg = <1>;
67	};
68	phy2: ethernet-phy@2 {
69		reg = <2>;
70	};
71	phy3: ethernet-phy@3 {
72		reg = <3>;
73	};
74	phy4: ethernet-phy@4 {
75		reg = <4>;
76	};
77	phy5: ethernet-phy@5 {
78		reg = <5>;
79	};
80	phy6: ethernet-phy@6 {
81		reg = <6>;
82	};
83	phy7: ethernet-phy@7 {
84		reg = <7>;
85	};
86	phy8: ethernet-phy@8 {
87		reg = <8>;
88	};
89	phy9: ethernet-phy@9 {
90		reg = <9>;
91	};
92	phy10: ethernet-phy@10 {
93		reg = <10>;
94	};
95	phy11: ethernet-phy@11 {
96		reg = <11>;
97	};
98};
99
100&mdio1 {
101	status = "okay";
102
103	phy12: ethernet-phy@12 {
104		reg = <0>;
105	};
106	phy13: ethernet-phy@13 {
107		reg = <1>;
108	};
109	phy14: ethernet-phy@14 {
110		reg = <2>;
111	};
112	phy15: ethernet-phy@15 {
113		reg = <3>;
114	};
115	phy16: ethernet-phy@16 {
116		reg = <4>;
117	};
118	phy17: ethernet-phy@17 {
119		reg = <5>;
120	};
121	phy18: ethernet-phy@18 {
122		reg = <6>;
123	};
124	phy19: ethernet-phy@19 {
125		reg = <7>;
126	};
127	phy20: ethernet-phy@20 {
128		reg = <8>;
129	};
130	phy21: ethernet-phy@21 {
131		reg = <9>;
132	};
133	phy22: ethernet-phy@22 {
134		reg = <10>;
135	};
136	phy23: ethernet-phy@23 {
137		reg = <11>;
138	};
139};
140
141&switch {
142	ethernet-ports {
143		port0: port@0 {
144			reg = <0>;
145			phy-handle = <&phy0>;
146		};
147		port1: port@1 {
148			reg = <1>;
149			phy-handle = <&phy1>;
150		};
151		port2: port@2 {
152			reg = <2>;
153			phy-handle = <&phy2>;
154		};
155		port3: port@3 {
156			reg = <3>;
157			phy-handle = <&phy3>;
158		};
159		port4: port@4 {
160			reg = <4>;
161			phy-handle = <&phy4>;
162		};
163		port5: port@5 {
164			reg = <5>;
165			phy-handle = <&phy5>;
166		};
167		port6: port@6 {
168			reg = <6>;
169			phy-handle = <&phy6>;
170		};
171		port7: port@7 {
172			reg = <7>;
173			phy-handle = <&phy7>;
174		};
175		port8: port@8 {
176			reg = <8>;
177			phy-handle = <&phy8>;
178		};
179		port9: port@9 {
180			reg = <9>;
181			phy-handle = <&phy9>;
182		};
183		port10: port@10 {
184			reg = <10>;
185			phy-handle = <&phy10>;
186		};
187		port11: port@11 {
188			reg = <11>;
189			phy-handle = <&phy11>;
190		};
191		port12: port@12 {
192			reg = <12>;
193			phy-handle = <&phy12>;
194			phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>;
195		};
196		port13: port@13 {
197			reg = <13>;
198			phy-handle = <&phy13>;
199			phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
200		};
201		port14: port@14 {
202			reg = <14>;
203			phy-handle = <&phy14>;
204			phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
205		};
206		port15: port@15 {
207			reg = <15>;
208			phy-handle = <&phy15>;
209			phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
210		};
211		port16: port@16 {
212			reg = <16>;
213			phy-handle = <&phy16>;
214			phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>;
215		};
216		port17: port@17 {
217			reg = <17>;
218			phy-handle = <&phy17>;
219			phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
220		};
221		port18: port@18 {
222			reg = <18>;
223			phy-handle = <&phy18>;
224			phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
225		};
226		port19: port@19 {
227			reg = <19>;
228			phy-handle = <&phy19>;
229			phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
230		};
231		port20: port@20 {
232			reg = <20>;
233			phy-handle = <&phy20>;
234			phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>;
235		};
236		port21: port@21 {
237			reg = <21>;
238			phy-handle = <&phy21>;
239			phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
240		};
241		port22: port@22 {
242			reg = <22>;
243			phy-handle = <&phy22>;
244			phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
245		};
246		port23: port@23 {
247			reg = <23>;
248			phy-handle = <&phy23>;
249			phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
250		};
251	};
252};
253