1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/ {
7	#address-cells = <1>;
8	#size-cells = <1>;
9	compatible = "mscc,ocelot";
10
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			compatible = "mips,mips24KEc";
17			device_type = "cpu";
18			clocks = <&cpu_clk>;
19			reg = <0>;
20		};
21	};
22
23	aliases {
24		serial0 = &uart0;
25	};
26
27	cpuintc: interrupt-controller@0 {
28		#address-cells = <0>;
29		#interrupt-cells = <1>;
30		interrupt-controller;
31		compatible = "mti,cpu-interrupt-controller";
32	};
33
34	cpu_clk: cpu-clock {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <500000000>;
38	};
39
40	sys_clk: sys-clk {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <250000000>;
44	};
45
46	ahb_clk: ahb-clk {
47		compatible = "fixed-clock";
48		#clock-cells = <0>;
49		clock-frequency = <250000000>;
50	};
51
52	ahb {
53		compatible = "simple-bus";
54		#address-cells = <1>;
55		#size-cells = <1>;
56		ranges = <0 0x70000000 0x2000000>;
57
58		interrupt-parent = <&intc>;
59
60		cpu_ctrl: syscon@0 {
61			compatible = "mscc,ocelot-cpu-syscon", "syscon";
62			reg = <0x0 0x2c>;
63		};
64
65		intc: interrupt-controller@70 {
66			compatible = "mscc,ocelot-icpu-intr";
67			reg = <0x70 0x70>;
68			#interrupt-cells = <1>;
69			interrupt-controller;
70			interrupt-parent = <&cpuintc>;
71			interrupts = <2>;
72		};
73
74		uart0: serial@100000 {
75			pinctrl-0 = <&uart_pins>;
76			pinctrl-names = "default";
77			compatible = "ns16550a";
78			reg = <0x100000 0x20>;
79			interrupts = <6>;
80			clocks = <&ahb_clk>;
81			reg-io-width = <4>;
82			reg-shift = <2>;
83
84			status = "disabled";
85		};
86
87		uart2: serial@100800 {
88			pinctrl-0 = <&uart2_pins>;
89			pinctrl-names = "default";
90			compatible = "ns16550a";
91			reg = <0x100800 0x20>;
92			interrupts = <7>;
93			clocks = <&ahb_clk>;
94			reg-io-width = <4>;
95			reg-shift = <2>;
96
97			status = "disabled";
98		};
99
100		spi0: spi-master@101000 {
101			#address-cells = <1>;
102			#size-cells = <0>;
103			compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
104			reg = <0x101000 0x40>;
105			num-chipselect = <4>;
106			bus-num = <0>;
107			reg-io-width = <4>;
108			reg-shift = <2>;
109			spi-max-frequency = <18000000>; /* input clock */
110			clocks = <&ahb_clk>;
111
112			status = "disabled";
113		};
114
115		switch: switch@1010000 {
116			pinctrl-0 = <&miim1_pins>;
117			pinctrl-names = "default";
118
119			compatible = "mscc,vsc7514-switch";
120
121			reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0
122			      <0x11f0000 0x100>, // VTSS_TO_DEV_1
123			      <0x1200000 0x100>, // VTSS_TO_DEV_2
124			      <0x1210000 0x100>, // VTSS_TO_DEV_3
125			      <0x1220000 0x100>, // VTSS_TO_DEV_4
126			      <0x1230000 0x100>, // VTSS_TO_DEV_5
127			      <0x1240000 0x100>, // VTSS_TO_DEV_6
128			      <0x1250000 0x100>, // VTSS_TO_DEV_7
129			      <0x1260000 0x100>, // VTSS_TO_DEV_8
130			      <0x1270000 0x100>, // VTSS_TO_DEV_9
131			      <0x1280000 0x100>, // VTSS_TO_DEV_10
132			      <0x1010000 0x10000>, // VTSS_TO_SYS
133			      <0x1030000 0x10000>, // VTSS_TO_REW
134			      <0x1080000 0x100>, // VTSS_TO_DEVCPU_QS
135			      <0x10d0000 0x10000>, // VTSS_TO_HSIO
136			      <0x1800000 0x80000>,// VTSS_TO_QSYS
137			      <0x1880000 0x10000>;// VTSS_TO_ANA
138			reg-names = "port0", "port1", "port2", "port3", "port4",
139				    "port5", "port6", "port7", "port8", "port9",
140				    "port10",
141				    "sys", "rew", "qs", "hsio", "qsys", "ana";
142			interrupts = <21 22>;
143			interrupt-names = "xtr", "inj";
144			status = "okay";
145
146			ethernet-ports {
147				#address-cells = <1>;
148				#size-cells = <0>;
149			};
150		};
151
152		mdio0: mdio@107009c {
153			#address-cells = <1>;
154			#size-cells = <0>;
155			compatible = "mscc,ocelot-miim";
156			reg = <0x107009c 0x24>;
157			interrupts = <14>;
158			status = "disabled";
159		};
160
161		mdio1: mdio@10700f0 {
162			#address-cells = <1>;
163			#size-cells = <0>;
164			compatible = "mscc,ocelot-miim";
165			reg = <0x10700c0 0x24>;
166			interrupts = <14>;
167			status = "disabled";
168		};
169
170		hsio: syscon@10d0000 {
171			compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
172			reg = <0x10d0000 0x10000>;
173
174			serdes_hsio: serdes_hsio {
175				compatible = "mscc,vsc7514-serdes";
176				#phy-cells = <3>;
177			};
178		};
179
180		reset@1070008 {
181			compatible = "mscc,ocelot-chip-reset";
182			reg = <0x1070008 0x4>;
183		};
184
185		gpio: pinctrl@1070034 {
186			compatible = "mscc,ocelot-pinctrl";
187			reg = <0x1070034 0x68>;
188			gpio-controller;
189			#gpio-cells = <2>;
190			gpio-ranges = <&gpio 0 0 22>;
191
192			sgpio_pins: sgpio-pins {
193				pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
194				function = "sg0";
195			};
196
197			uart_pins: uart-pins {
198				pins = "GPIO_6", "GPIO_7";
199				function = "uart";
200			};
201
202			uart2_pins: uart2-pins {
203				pins = "GPIO_12", "GPIO_13";
204				function = "uart2";
205			};
206
207			spi_cs1_pin: spi-cs1-pin {
208				pins = "GPIO_8";
209				function = "si";
210			};
211
212			miim1_pins: miim1-pins {
213				pins = "GPIO_14", "GPIO_15";
214				function = "miim1";
215			};
216
217			spi_cs2_pin: spi-cs2-pin {
218				pins = "GPIO_9";
219				function = "si";
220			};
221
222			spi_cs3_pin: spi-cs3-pin {
223				pins = "GPIO_16";
224				function = "si";
225			};
226
227			spi_cs4_pin: spi-cs4-pin {
228				pins = "GPIO_17";
229				function = "si";
230			};
231		};
232
233		sgpio: gpio@10700f8 {
234			compatible = "mscc,ocelot-sgpio";
235			status = "disabled";
236			clocks = <&sys_clk>;
237			pinctrl-0 = <&sgpio_pins>;
238			pinctrl-names = "default";
239			reg = <0x10700f8 0x100>;
240			gpio-controller;
241			#gpio-cells = <2>;
242			gpio-ranges = <&sgpio 0 0 64>;
243		};
244	};
245};
246