1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/ {
7	#address-cells = <1>;
8	#size-cells = <1>;
9	compatible = "mscc,serval";
10
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			compatible = "mips,mips24KEc";
17			device_type = "cpu";
18			clocks = <&cpu_clk>;
19			reg = <0>;
20		};
21	};
22
23	aliases {
24		serial0 = &uart0;
25	};
26
27	cpuintc: interrupt-controller@0 {
28		#address-cells = <0>;
29		#interrupt-cells = <1>;
30		interrupt-controller;
31		compatible = "mti,cpu-interrupt-controller";
32	};
33
34	cpu_clk: cpu-clock {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <416666666>;
38	};
39
40	sys_clk: sys-clk {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <208333333>;
44	};
45
46	ahb_clk: ahb-clk {
47		compatible = "fixed-clock";
48		#clock-cells = <0>;
49		clock-frequency = <208333333>;
50	};
51
52	ahb {
53		compatible = "simple-bus";
54		#address-cells = <1>;
55		#size-cells = <1>;
56		ranges = <0 0x70000000 0x2000000>;
57
58		interrupt-parent = <&intc>;
59
60		cpu_ctrl: syscon@0 {
61			compatible = "mscc,serval-cpu-syscon", "syscon";
62			reg = <0x0 0x2c>;
63		};
64
65		intc: interrupt-controller@70 {
66			compatible = "mscc,serval-icpu-intr";
67			reg = <0x70 0x70>;
68			#interrupt-cells = <1>;
69			interrupt-controller;
70			interrupt-parent = <&cpuintc>;
71			interrupts = <2>;
72		};
73
74		uart0: serial@100000 {
75			pinctrl-0 = <&uart_pins>;
76			pinctrl-names = "default";
77			compatible = "ns16550a";
78			reg = <0x100000 0x20>;
79			interrupts = <6>;
80			clocks = <&ahb_clk>;
81			reg-io-width = <4>;
82			reg-shift = <2>;
83
84			status = "disabled";
85		};
86
87		uart2: serial@100800 {
88			pinctrl-0 = <&uart2_pins>;
89			pinctrl-names = "default";
90			compatible = "ns16550a";
91			reg = <0x100800 0x20>;
92			interrupts = <7>;
93			clocks = <&ahb_clk>;
94			reg-io-width = <4>;
95			reg-shift = <2>;
96
97			status = "disabled";
98		};
99
100		reset@1070008 {
101			compatible = "mscc,serval-chip-reset";
102			reg = <0x1070008 0x4>;
103		};
104
105		gpio: pinctrl@1070034 {
106			compatible = "mscc,serval-pinctrl";
107			reg = <0x1070034 0x68>;
108			gpio-controller;
109			#gpio-cells = <2>;
110			gpio-ranges = <&gpio 0 0 22>;
111
112			sgpio_pins: sgpio-pins {
113				pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
114				function = "sio";
115			};
116
117			uart_pins: uart-pins {
118				pins = "GPIO_26", "GPIO_27";
119				function = "uart";
120			};
121
122			uart2_pins: uart2-pins {
123				pins = "GPIO_13", "GPIO_14";
124				function = "uart2";
125			};
126		};
127
128		spi0: spi-bitbang {
129			compatible = "mscc,luton-bb-spi";
130			status = "okay";
131			reg = <0x50 0x4>;
132			num-chipselects = <1>;
133			#address-cells = <1>;
134			#size-cells = <0>;
135		};
136
137		sgpio: gpio@10700b4 {
138			compatible = "mscc,luton-sgpio";
139			status = "disabled";
140			clocks = <&sys_clk>;
141			pinctrl-0 = <&sgpio_pins>;
142			pinctrl-names = "default";
143			reg = <0x10700b4 0x100>;
144			gpio-controller;
145			#gpio-cells = <2>;
146			gpio-ranges = <&sgpio 0 0 64>;
147		};
148
149		switch: switch@011e0000 {
150			compatible = "mscc,vsc7418-switch";
151			reg = <0x011e0000 0x0100>,   // VTSS_TO_DEV0
152			      <0x011f0000 0x0100>,   // VTSS_TO_DEV1
153			      <0x01200000 0x0100>,   // VTSS_TO_DEV2
154			      <0x01210000 0x0100>,   // VTSS_TO_DEV3
155			      <0x01220000 0x0100>,   // VTSS_TO_DEV4
156			      <0x01230000 0x0100>,   // VTSS_TO_DEV5
157			      <0x01240000 0x0100>,   // VTSS_TO_DEV6
158			      <0x01250000 0x0100>,   // VTSS_TO_DEV7
159			      <0x01260000 0x0100>,   // VTSS_TO_DEV8
160			      <0x01270000 0x0100>,   // VTSS_TO_DEV9
161			      <0x01280000 0x0100>,   // VTSS_TO_DEV10
162			      <0x01900000 0x100000>, // ANA
163			      <0x01080000 0x20000>,  // QS
164			      <0x01800000 0x100000>, // QSYS
165			      <0x01030000 0x10000>,  // REW
166			      <0x01010000 0x20000>,  // SYS
167			      <0x010a0000 0x10000>;  // HSIO
168			reg-names = "port0", "port1", "port2", "port3",
169				    "port4", "port5", "port6", "port7",
170				    "port8", "port9", "port10",
171				    "ana", "qs", "qsys", "rew", "sys",
172				    "hsio";
173			status = "okay";
174
175			ethernet-ports {
176				#address-cells = <1>;
177				#size-cells = <0>;
178			};
179		};
180
181		mdio0: mdio@0107005c {
182			#address-cells = <1>;
183			#size-cells = <0>;
184			compatible = "mscc,serval-miim";
185			reg = <0x0107005c 0x24>;
186			status = "disabled";
187		};
188
189		mdio1: mdio@01070080 {
190			#address-cells = <1>;
191			#size-cells = <0>;
192			compatible = "mscc,serval-miim";
193			reg = <0x01070080 0x24>;
194			status = "disabled";
195		};
196
197		hsio: syscon@10d0000 {
198			compatible = "mscc,serval-hsio", "syscon", "simple-mfd";
199			reg = <0x10a0000 0x10000>;
200
201			serdes_hsio: serdes_hsio {
202				compatible = "mscc,vsc7418-serdes";
203				#phy-cells = <3>;
204			};
205		};
206	};
207};
208