1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Cache operations for the cache instruction.
4 *
5 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
6 * (C) Copyright 1999 Silicon Graphics, Inc.
7 */
8 #ifndef __ASM_CACHEOPS_H
9 #define __ASM_CACHEOPS_H
10
11 #include <asm/cache.h>
12
13 #ifndef __ASSEMBLY__
14
mips_cache(int op,const volatile void * addr)15 static inline void mips_cache(int op, const volatile void *addr)
16 {
17 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
18 __builtin_mips_cache(op, addr);
19 #else
20 __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
21 #endif
22 }
23
24 #define MIPS32_WHICH_ICACHE 0x0
25 #define MIPS32_FETCH_AND_LOCK 0x7
26
27 #define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
28
29 /* Prefetch and lock instructions into cache */
icache_lock(void * func,size_t len)30 static inline void icache_lock(void *func, size_t len)
31 {
32 int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
33
34 for (i = 0; i < lines; i++) {
35 asm volatile (" cache %0, %1(%2)"
36 : /* No Output */
37 : "I" ICACHE_LOAD_LOCK,
38 "n" (i * ARCH_DMA_MINALIGN),
39 "r" (func)
40 : /* No Clobbers */);
41 }
42 }
43 #endif /* !__ASSEMBLY__ */
44
45 /*
46 * Cache Operations available on all MIPS processors with R4000-style caches
47 */
48 #define INDEX_INVALIDATE_I 0x00
49 #define INDEX_WRITEBACK_INV_D 0x01
50 #define INDEX_LOAD_TAG_I 0x04
51 #define INDEX_LOAD_TAG_D 0x05
52 #define INDEX_STORE_TAG_I 0x08
53 #define INDEX_STORE_TAG_D 0x09
54 #if defined(CONFIG_CPU_LOONGSON2)
55 #define HIT_INVALIDATE_I 0x00
56 #else
57 #define HIT_INVALIDATE_I 0x10
58 #endif
59 #define HIT_INVALIDATE_D 0x11
60 #define HIT_WRITEBACK_INV_D 0x15
61
62 /*
63 * R4000-specific cacheops
64 */
65 #define CREATE_DIRTY_EXCL_D 0x0d
66 #define FILL 0x14
67 #define HIT_WRITEBACK_I 0x18
68 #define HIT_WRITEBACK_D 0x19
69
70 /*
71 * R4000SC and R4400SC-specific cacheops
72 */
73 #define INDEX_INVALIDATE_SI 0x02
74 #define INDEX_WRITEBACK_INV_SD 0x03
75 #define INDEX_LOAD_TAG_SI 0x06
76 #define INDEX_LOAD_TAG_SD 0x07
77 #define INDEX_STORE_TAG_SI 0x0A
78 #define INDEX_STORE_TAG_SD 0x0B
79 #define CREATE_DIRTY_EXCL_SD 0x0f
80 #define HIT_INVALIDATE_SI 0x12
81 #define HIT_INVALIDATE_SD 0x13
82 #define HIT_WRITEBACK_INV_SD 0x17
83 #define HIT_WRITEBACK_SD 0x1b
84 #define HIT_SET_VIRTUAL_SI 0x1e
85 #define HIT_SET_VIRTUAL_SD 0x1f
86
87 /*
88 * R5000-specific cacheops
89 */
90 #define R5K_PAGE_INVALIDATE_S 0x17
91
92 /*
93 * RM7000-specific cacheops
94 */
95 #define PAGE_INVALIDATE_T 0x16
96
97 /*
98 * R10000-specific cacheops
99 *
100 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
101 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
102 */
103 #define INDEX_WRITEBACK_INV_S 0x03
104 #define INDEX_LOAD_TAG_S 0x07
105 #define INDEX_STORE_TAG_S 0x0B
106 #define HIT_INVALIDATE_S 0x13
107 #define CACHE_BARRIER 0x14
108 #define HIT_WRITEBACK_INV_S 0x17
109 #define INDEX_LOAD_DATA_I 0x18
110 #define INDEX_LOAD_DATA_D 0x19
111 #define INDEX_LOAD_DATA_S 0x1b
112 #define INDEX_STORE_DATA_I 0x1c
113 #define INDEX_STORE_DATA_D 0x1d
114 #define INDEX_STORE_DATA_S 0x1f
115
116 #endif /* __ASM_CACHEOPS_H */
117