1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2003
4 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <asm/cache.h>
10 #include <asm/cacheops.h>
11 #include <asm/cm.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <asm/mipsregs.h>
15 #include <asm/system.h>
16 #include <linux/bug.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
probe_l2(void)20 static void probe_l2(void)
21 {
22 #ifdef CONFIG_MIPS_L2_CACHE
23 unsigned long conf2, sl;
24 bool l2c = false;
25
26 if (!(read_c0_config1() & MIPS_CONF_M))
27 return;
28
29 conf2 = read_c0_config2();
30
31 if (__mips_isa_rev >= 6) {
32 l2c = conf2 & MIPS_CONF_M;
33 if (l2c)
34 l2c = read_c0_config3() & MIPS_CONF_M;
35 if (l2c)
36 l2c = read_c0_config4() & MIPS_CONF_M;
37 if (l2c)
38 l2c = read_c0_config5() & MIPS_CONF5_L2C;
39 }
40
41 if (l2c && config_enabled(CONFIG_MIPS_CM)) {
42 gd->arch.l2_line_size = mips_cm_l2_line_size();
43 } else if (l2c) {
44 /* We don't know how to retrieve L2 config on this system */
45 BUG();
46 } else {
47 sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
48 gd->arch.l2_line_size = sl ? (2 << sl) : 0;
49 }
50 #endif
51 }
52
mips_cache_probe(void)53 void mips_cache_probe(void)
54 {
55 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
56 unsigned long conf1, il, dl;
57
58 conf1 = read_c0_config1();
59
60 il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
61 dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
62
63 gd->arch.l1i_line_size = il ? (2 << il) : 0;
64 gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
65 #endif
66 probe_l2();
67 }
68
icache_line_size(void)69 static inline unsigned long icache_line_size(void)
70 {
71 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
72 return gd->arch.l1i_line_size;
73 #else
74 return CONFIG_SYS_ICACHE_LINE_SIZE;
75 #endif
76 }
77
dcache_line_size(void)78 static inline unsigned long dcache_line_size(void)
79 {
80 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
81 return gd->arch.l1d_line_size;
82 #else
83 return CONFIG_SYS_DCACHE_LINE_SIZE;
84 #endif
85 }
86
scache_line_size(void)87 static inline unsigned long scache_line_size(void)
88 {
89 #ifdef CONFIG_MIPS_L2_CACHE
90 return gd->arch.l2_line_size;
91 #else
92 return CONFIG_SYS_SCACHE_LINE_SIZE;
93 #endif
94 }
95
96 #define cache_loop(start, end, lsize, ops...) do { \
97 const void *addr = (const void *)(start & ~(lsize - 1)); \
98 const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
99 const unsigned int cache_ops[] = { ops }; \
100 unsigned int i; \
101 \
102 if (!lsize) \
103 break; \
104 \
105 for (; addr <= aend; addr += lsize) { \
106 for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
107 mips_cache(cache_ops[i], addr); \
108 } \
109 } while (0)
110
flush_cache(ulong start_addr,ulong size)111 void __weak flush_cache(ulong start_addr, ulong size)
112 {
113 unsigned long ilsize = icache_line_size();
114 unsigned long dlsize = dcache_line_size();
115 unsigned long slsize = scache_line_size();
116
117 /* aend will be miscalculated when size is zero, so we return here */
118 if (size == 0)
119 return;
120
121 if ((ilsize == dlsize) && !slsize) {
122 /* flush I-cache & D-cache simultaneously */
123 cache_loop(start_addr, start_addr + size, ilsize,
124 HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
125 goto ops_done;
126 }
127
128 /* flush D-cache */
129 cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
130
131 /* flush L2 cache */
132 cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
133
134 /* flush I-cache */
135 cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
136
137 ops_done:
138 /* ensure cache ops complete before any further memory accesses */
139 sync();
140
141 /* ensure the pipeline doesn't contain now-invalid instructions */
142 instruction_hazard_barrier();
143 }
144
flush_dcache_range(ulong start_addr,ulong stop)145 void __weak flush_dcache_range(ulong start_addr, ulong stop)
146 {
147 unsigned long lsize = dcache_line_size();
148 unsigned long slsize = scache_line_size();
149
150 /* aend will be miscalculated when size is zero, so we return here */
151 if (start_addr == stop)
152 return;
153
154 cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
155
156 /* flush L2 cache */
157 cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
158
159 /* ensure cache ops complete before any further memory accesses */
160 sync();
161 }
162
invalidate_dcache_range(ulong start_addr,ulong stop)163 void __weak invalidate_dcache_range(ulong start_addr, ulong stop)
164 {
165 unsigned long lsize = dcache_line_size();
166 unsigned long slsize = scache_line_size();
167
168 /* aend will be miscalculated when size is zero, so we return here */
169 if (start_addr == stop)
170 return;
171
172 /* invalidate L2 cache */
173 cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
174
175 cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
176
177 /* ensure cache ops complete before any further memory accesses */
178 sync();
179 }
180
dcache_status(void)181 int dcache_status(void)
182 {
183 unsigned int cca = read_c0_config() & CONF_CM_CMASK;
184 return cca != CONF_CM_UNCACHED;
185 }
186
dcache_enable(void)187 void dcache_enable(void)
188 {
189 puts("Not supported!\n");
190 }
191
dcache_disable(void)192 void dcache_disable(void)
193 {
194 /* change CCA to uncached */
195 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
196
197 /* ensure the pipeline doesn't contain now-invalid instructions */
198 instruction_hazard_barrier();
199 }
200