1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2007
4 *
5 * Author: Scott Wood <scottwood@freescale.com>,
6 * with some bits from older board-specific PCI initialization.
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <pci.h>
12 #include <asm/bitops.h>
13 #include <asm/global_data.h>
14 #include <linux/delay.h>
15
16 #if defined(CONFIG_OF_LIBFDT)
17 #include <linux/libfdt.h>
18 #include <fdt_support.h>
19 #endif
20
21 #include <asm/mpc8349_pci.h>
22
23 #define MAX_BUSES 2
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 static struct pci_controller pci_hose[MAX_BUSES];
28 static int pci_num_buses;
29
pci_init_bus(int bus,struct pci_region * reg)30 static void pci_init_bus(int bus, struct pci_region *reg)
31 {
32 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
33 volatile pot83xx_t *pot = immr->ios.pot;
34 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
35 struct pci_controller *hose = &pci_hose[bus];
36 u32 dev;
37 u16 reg16;
38 int i;
39
40 if (bus == 1)
41 pot += 3;
42
43 /* Setup outbound translation windows */
44 for (i = 0; i < 3; i++, reg++, pot++) {
45 if (reg->size == 0)
46 break;
47
48 hose->regions[i] = *reg;
49 hose->region_count++;
50
51 pot->potar = reg->bus_start >> 12;
52 pot->pobar = reg->phys_start >> 12;
53 pot->pocmr = ~(reg->size - 1) >> 12;
54
55 if (reg->flags & PCI_REGION_IO)
56 pot->pocmr |= POCMR_IO;
57 #ifdef CONFIG_83XX_PCI_STREAMING
58 else if (reg->flags & PCI_REGION_PREFETCH)
59 pot->pocmr |= POCMR_SE;
60 #endif
61
62 if (bus == 1)
63 pot->pocmr |= POCMR_DST;
64
65 pot->pocmr |= POCMR_EN;
66 }
67
68 /* Point inbound translation at RAM */
69 pci_ctrl->pitar1 = 0;
70 pci_ctrl->pibar1 = 0;
71 pci_ctrl->piebar1 = 0;
72 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
73 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
74
75 i = hose->region_count++;
76 hose->regions[i].bus_start = 0;
77 hose->regions[i].phys_start = 0;
78 hose->regions[i].size = gd->ram_size;
79 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
80
81 hose->first_busno = pci_last_busno() + 1;
82 hose->last_busno = 0xff;
83
84 pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
85 CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
86
87 pci_register_hose(hose);
88
89 /*
90 * Write to Command register
91 */
92 reg16 = 0xff;
93 dev = PCI_BDF(hose->first_busno, 0, 0);
94 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
95 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
96 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
97
98 /*
99 * Clear non-reserved bits in status register.
100 */
101 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
102 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
103 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
104
105 #ifdef CONFIG_PCI_SCAN_SHOW
106 printf("PCI: Bus Dev VenId DevId Class Int\n");
107 #endif
108 #ifndef CONFIG_PCISLAVE
109 /*
110 * Hose scan.
111 */
112 hose->last_busno = pci_hose_scan(hose);
113 #endif
114 }
115
116 /*
117 * The caller must have already set OCCR, and the PCI_LAW BARs
118 * must have been set to cover all of the requested regions.
119 *
120 * If fewer than three regions are requested, then the region
121 * list is terminated with a region of size 0.
122 */
mpc83xx_pci_init(int num_buses,struct pci_region ** reg)123 void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
124 {
125 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
126 int i;
127
128 if (num_buses > MAX_BUSES) {
129 printf("%d PCI buses requested, %d supported\n",
130 num_buses, MAX_BUSES);
131
132 num_buses = MAX_BUSES;
133 }
134
135 pci_num_buses = num_buses;
136
137 /*
138 * Release PCI RST Output signal.
139 * Power on to RST high must be at least 100 ms as per PCI spec.
140 * On warm boots only 1 ms is required, but we play it safe.
141 */
142 udelay(100000);
143
144 for (i = 0; i < num_buses; i++)
145 immr->pci_ctrl[i].gcr = 1;
146
147 /*
148 * RST high to first config access must be at least 2^25 cycles
149 * as per PCI spec. This could be cut in half if we know we're
150 * running at 66MHz. This could be insufficiently long if we're
151 * running the PCI bus at significantly less than 33MHz.
152 */
153 udelay(1020000);
154
155 for (i = 0; i < num_buses; i++)
156 pci_init_bus(i, reg[i]);
157 }
158
159 #ifdef CONFIG_PCISLAVE
160
161 #define PCI_FUNCTION_CONFIG 0x44
162 #define PCI_FUNCTION_CFG_LOCK 0x20
163
164 /*
165 * Unlock the configuration bit so that the host system can begin booting
166 *
167 * This should be used after you have:
168 * 1) Called mpc83xx_pci_init()
169 * 2) Set up your inbound translation windows to the appropriate size
170 */
mpc83xx_pcislave_unlock(int bus)171 void mpc83xx_pcislave_unlock(int bus)
172 {
173 struct pci_controller *hose = &pci_hose[bus];
174 u32 dev;
175 u16 reg16;
176
177 /* Unlock configuration lock in PCI function configuration register */
178 dev = PCI_BDF(hose->first_busno, 0, 0);
179 pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16);
180 reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
181 pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
182
183 /* The configuration bit is now unlocked, so we can scan the bus */
184 hose->last_busno = pci_hose_scan(hose);
185 }
186 #endif
187
188 #if defined(CONFIG_OF_LIBFDT)
ft_pci_setup(void * blob,struct bd_info * bd)189 void ft_pci_setup(void *blob, struct bd_info *bd)
190 {
191 int nodeoffset;
192 int tmp[2];
193 const char *path;
194
195 if (pci_num_buses < 1)
196 return;
197
198 nodeoffset = fdt_path_offset(blob, "/aliases");
199 if (nodeoffset >= 0) {
200 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
201 if (path) {
202 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
203 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
204 do_fixup_by_path(blob, path, "bus-range",
205 &tmp, sizeof(tmp), 1);
206
207 tmp[0] = cpu_to_be32(gd->pci_clk);
208 do_fixup_by_path(blob, path, "clock-frequency",
209 &tmp, sizeof(tmp[0]), 1);
210 }
211
212 if (pci_num_buses < 2)
213 return;
214
215 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
216 if (path) {
217 tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
218 tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
219 do_fixup_by_path(blob, path, "bus-range",
220 &tmp, sizeof(tmp), 1);
221
222 tmp[0] = cpu_to_be32(gd->pci_clk);
223 do_fixup_by_path(blob, path, "clock-frequency",
224 &tmp, sizeof(tmp[0]), 1);
225 }
226 }
227 }
228 #endif /* CONFIG_OF_LIBFDT */
229