1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 4 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 5 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 6 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 7 */ 8 9/* 10 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 11 */ 12 13#include <asm-offsets.h> 14#include <config.h> 15#include <mpc83xx.h> 16#include <version.h> 17 18#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 19 20#include <ppc_asm.tmpl> 21#include <ppc_defs.h> 22 23#include <asm/cache.h> 24#include <asm/mmu.h> 25#include <asm/u-boot.h> 26 27#include "hrcw/hrcw.h" 28#include "bats/bats.h" 29#include "hid/hid.h" 30 31/* We don't want the MMU yet. 32 */ 33#undef MSR_KERNEL 34 35/* 36 * Floating Point enable, Machine Check and Recoverable Interr. 37 */ 38#ifdef DEBUG 39#define MSR_KERNEL (MSR_FP|MSR_RI) 40#else 41#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 42#endif 43 44#if defined(CONFIG_NAND_SPL) || \ 45 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 46#define MINIMAL_SPL 47#endif 48 49#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ 50 !defined(CONFIG_SYS_RAMBOOT) 51#define CONFIG_SYS_FLASHBOOT 52#endif 53 54/* 55 * Set up GOT: Global Offset Table 56 * 57 * Use r12 to access the GOT 58 */ 59 START_GOT 60 GOT_ENTRY(_GOT2_TABLE_) 61 GOT_ENTRY(__bss_start) 62 GOT_ENTRY(__bss_end) 63 64#ifndef MINIMAL_SPL 65 GOT_ENTRY(_FIXUP_TABLE_) 66 GOT_ENTRY(_start) 67 GOT_ENTRY(_start_of_vectors) 68 GOT_ENTRY(_end_of_vectors) 69 GOT_ENTRY(transfer_to_handler) 70#endif 71 END_GOT 72 73/* 74 * The Hard Reset Configuration Word (HRCW) table is in the first 64 75 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 76 * times so the processor can fetch it out of flash whether the flash 77 * is 8, 16, 32, or 64 bits wide (hardware trickery). 78 */ 79 .text 80#define _HRCW_TABLE_ENTRY(w) \ 81 .fill 8,1,(((w)>>24)&0xff); \ 82 .fill 8,1,(((w)>>16)&0xff); \ 83 .fill 8,1,(((w)>> 8)&0xff); \ 84 .fill 8,1,(((w) )&0xff) 85 86 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 87 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 88 89/* 90 * Magic number and version string - put it after the HRCW since it 91 * cannot be first in flash like it is in many other processors. 92 */ 93 .long 0x27051956 /* U-Boot Magic Number */ 94 95 .globl version_string 96version_string: 97 .ascii U_BOOT_VERSION_STRING, "\0" 98 99 .align 2 100 101 .globl enable_addr_trans 102enable_addr_trans: 103 /* enable address translation */ 104 mfmsr r5 105 ori r5, r5, (MSR_IR | MSR_DR) 106 mtmsr r5 107 isync 108 blr 109 110 .globl disable_addr_trans 111disable_addr_trans: 112 /* disable address translation */ 113 mflr r4 114 mfmsr r3 115 andi. r0, r3, (MSR_IR | MSR_DR) 116 beqlr 117 andc r3, r3, r0 118 mtspr SRR0, r4 119 mtspr SRR1, r3 120 rfi 121 122#ifndef CONFIG_DEFAULT_IMMR 123#error CONFIG_DEFAULT_IMMR must be defined 124#endif /* CONFIG_DEFAULT_IMMR */ 125#ifndef CONFIG_SYS_IMMR 126#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 127#endif /* CONFIG_SYS_IMMR */ 128 129/* 130 * After configuration, a system reset exception is executed using the 131 * vector at offset 0x100 relative to the base set by MSR[IP]. If 132 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 133 * base address is 0xfff00000. In the case of a Power On Reset or Hard 134 * Reset, the value of MSR[IP] is determined by the CIP field in the 135 * HRCW. 136 * 137 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 138 * This determines the location of the boot ROM (flash or EPROM) in the 139 * processor's address space at boot time. As long as the HRCW is set up 140 * so that we eventually end up executing the code below when the 141 * processor executes the reset exception, the actual values used should 142 * not matter. 143 * 144 * Once we have got here, the address mask in OR0 is cleared so that the 145 * bottom 32K of the boot ROM is effectively repeated all throughout the 146 * processor's address space, after which we can jump to the absolute 147 * address at which the boot ROM was linked at compile time, and proceed 148 * to initialise the memory controller without worrying if the rug will 149 * be pulled out from under us, so to speak (it will be fine as long as 150 * we configure BR0 with the same boot ROM link address). 151 */ 152 . = EXC_OFF_SYS_RESET 153 154 .globl _start 155_start: /* time t 0 */ 156 lis r4, CONFIG_DEFAULT_IMMR@h 157 nop 158 159 mfmsr r5 /* save msr contents */ 160 161 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 162 bl 1f 1631: mflr r7 164 165 lis r3, CONFIG_SYS_IMMR@h 166 ori r3, r3, CONFIG_SYS_IMMR@l 167 168 lwz r6, IMMRBAR(r4) 169 isync 170 171 stw r3, IMMRBAR(r4) 172 lwz r6, 0(r7) /* Arbitrary external load */ 173 isync 174 175 lwz r6, IMMRBAR(r3) 176 isync 177 178 /* Initialise the E300 processor core */ 179 /*------------------------------------------*/ 180 181#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ 182 defined(CONFIG_NAND_SPL) 183 /* The FCM begins execution after only the first page 184 * is loaded. Wait for the rest before branching 185 * to another flash page. 186 */ 1871: lwz r6, 0x50b0(r3) 188 andi. r6, r6, 1 189 beq 1b 190#endif 191 192 bl init_e300_core 193 194#ifdef CONFIG_SYS_FLASHBOOT 195 196 /* Inflate flash location so it appears everywhere, calculate */ 197 /* the absolute address in final location of the FLASH, jump */ 198 /* there and deflate the flash size back to minimal size */ 199 /*------------------------------------------------------------*/ 200 bl map_flash_by_law1 201 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 202 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 203 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 204 mtlr r5 205 blr 206in_flash: 207#if 1 /* Remapping flash with LAW0. */ 208 bl remap_flash_by_law0 209#endif 210#endif /* CONFIG_SYS_FLASHBOOT */ 211 212 /* setup the bats */ 213 bl setup_bats 214 sync 215 216 /* 217 * Cache must be enabled here for stack-in-cache trick. 218 * This means we need to enable the BATS. 219 * This means: 220 * 1) for the EVB, original gt regs need to be mapped 221 * 2) need to have an IBAT for the 0xf region, 222 * we are running there! 223 * Cache should be turned on after BATs, since by default 224 * everything is write-through. 225 * The init-mem BAT can be reused after reloc. The old 226 * gt-regs BAT can be reused after board_init_f calls 227 * board_early_init_f (EVB only). 228 */ 229 /* enable address translation */ 230 bl enable_addr_trans 231 sync 232 233 /* enable the data cache */ 234 bl dcache_enable 235 sync 236#ifdef CONFIG_SYS_INIT_RAM_LOCK 237 bl lock_ram_in_cache 238 sync 239#endif 240 241 /* set up the stack pointer in our newly created 242 * cache-ram; use r3 to keep the new SP for now to 243 * avoid overiding the SP it uselessly */ 244 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 245 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 246 247 /* r4 = end of GD area */ 248 addi r4, r3, GENERATED_GBL_DATA_SIZE 249 250 /* Zero GD area */ 251 li r0, 0 2521: 253 subi r4, r4, 1 254 stb r0, 0(r4) 255 cmplw r3, r4 256 bne 1b 257 258#if CONFIG_VAL(SYS_MALLOC_F_LEN) 259 260#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE 261#error "SYS_MALLOC_F_LEN too large to fit into initial RAM." 262#endif 263 264 /* r3 = new stack pointer / pre-reloc malloc area */ 265 subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN) 266 267 /* Set pointer to pre-reloc malloc area in GD */ 268 stw r3, GD_MALLOC_BASE(r4) 269#endif 270 li r0, 0 /* Make room for stack frame header and */ 271 stwu r0, -4(r3) /* clear final stack frame so that */ 272 stwu r0, -4(r3) /* stack backtraces terminate cleanly */ 273 274 /* Finally, actually set SP */ 275 mr r1, r3 276 277 /* let the C-code set up the rest */ 278 /* */ 279 /* Be careful to keep code relocatable & stack humble */ 280 /*------------------------------------------------------*/ 281 282 GET_GOT /* initialize GOT access */ 283 /* Needed for -msingle-pic-base */ 284 bl _GLOBAL_OFFSET_TABLE_@local-4 285 mflr r30 286 287 /* r3: IMMR */ 288 lis r3, CONFIG_SYS_IMMR@h 289 /* run low-level CPU init code (in Flash)*/ 290 bl cpu_init_f 291 292 /* run 1st part of board init code (in Flash)*/ 293 li r3, 0 /* clear boot_flag for calling board_init_f */ 294 bl board_init_f 295 296 /* NOTREACHED - board_init_f() does not return */ 297 298#ifndef MINIMAL_SPL 299/* 300 * Vector Table 301 */ 302 303 .globl _start_of_vectors 304_start_of_vectors: 305 306/* Machine check */ 307 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 308 309/* Data Storage exception. */ 310 STD_EXCEPTION(0x300, DataStorage, UnknownException) 311 312/* Instruction Storage exception. */ 313 STD_EXCEPTION(0x400, InstStorage, UnknownException) 314 315/* External Interrupt exception. */ 316#ifndef FIXME 317 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 318#endif 319 320/* Alignment exception. */ 321 . = 0x600 322Alignment: 323 EXCEPTION_PROLOG(SRR0, SRR1) 324 mfspr r4,DAR 325 stw r4,_DAR(r21) 326 mfspr r5,DSISR 327 stw r5,_DSISR(r21) 328 addi r3,r1,STACK_FRAME_OVERHEAD 329 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 330 331/* Program check exception */ 332 . = 0x700 333ProgramCheck: 334 EXCEPTION_PROLOG(SRR0, SRR1) 335 addi r3,r1,STACK_FRAME_OVERHEAD 336 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 337 MSR_KERNEL, COPY_EE) 338 339 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 340 341 /* I guess we could implement decrementer, and may have 342 * to someday for timekeeping. 343 */ 344 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 345 346 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 347 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 348 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 349 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 350 351 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 352 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 353 354 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 355 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 356 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 357#ifdef DEBUG 358 . = 0x1300 359 /* 360 * This exception occurs when the program counter matches the 361 * Instruction Address Breakpoint Register (IABR). 362 * 363 * I want the cpu to halt if this occurs so I can hunt around 364 * with the debugger and look at things. 365 * 366 * When DEBUG is defined, both machine check enable (in the MSR) 367 * and checkstop reset enable (in the reset mode register) are 368 * turned off and so a checkstop condition will result in the cpu 369 * halting. 370 * 371 * I force the cpu into a checkstop condition by putting an illegal 372 * instruction here (at least this is the theory). 373 * 374 * well - that didnt work, so just do an infinite loop! 375 */ 3761: b 1b 377#else 378 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 379#endif 380 STD_EXCEPTION(0x1400, SMI, UnknownException) 381 382 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 383 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 384 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 385 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 386 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 387 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 388 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 389 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 390 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 391 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 392 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 393 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 394 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 395 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 396 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 397 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 398 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 399 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 400 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 401 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 402 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 403 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 404 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 405 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 406 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 407 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 408 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 409 410 411 .globl _end_of_vectors 412_end_of_vectors: 413 414 . = 0x3000 415 416/* 417 * This code finishes saving the registers to the exception frame 418 * and jumps to the appropriate handler for the exception. 419 * Register r21 is pointer into trap frame, r1 has new stack pointer. 420 */ 421 .globl transfer_to_handler 422transfer_to_handler: 423 stw r22,_NIP(r21) 424 lis r22,MSR_POW@h 425 andc r23,r23,r22 426 stw r23,_MSR(r21) 427 SAVE_GPR(7, r21) 428 SAVE_4GPRS(8, r21) 429 SAVE_8GPRS(12, r21) 430 SAVE_8GPRS(24, r21) 431 mflr r23 432 andi. r24,r23,0x3f00 /* get vector offset */ 433 stw r24,TRAP(r21) 434 li r22,0 435 stw r22,RESULT(r21) 436 lwz r24,0(r23) /* virtual address of handler */ 437 lwz r23,4(r23) /* where to go when done */ 438 mtspr SRR0,r24 439 mtspr SRR1,r20 440 mtlr r23 441 SYNC 442 rfi /* jump to handler, enable MMU */ 443 444int_return: 445 mfmsr r28 /* Disable interrupts */ 446 li r4,0 447 ori r4,r4,MSR_EE 448 andc r28,r28,r4 449 SYNC /* Some chip revs need this... */ 450 mtmsr r28 451 SYNC 452 lwz r2,_CTR(r1) 453 lwz r0,_LINK(r1) 454 mtctr r2 455 mtlr r0 456 lwz r2,_XER(r1) 457 lwz r0,_CCR(r1) 458 mtspr XER,r2 459 mtcrf 0xFF,r0 460 REST_10GPRS(3, r1) 461 REST_10GPRS(13, r1) 462 REST_8GPRS(23, r1) 463 REST_GPR(31, r1) 464 lwz r2,_NIP(r1) /* Restore environment */ 465 lwz r0,_MSR(r1) 466 mtspr SRR0,r2 467 mtspr SRR1,r0 468 lwz r0,GPR0(r1) 469 lwz r2,GPR2(r1) 470 lwz r1,GPR1(r1) 471 SYNC 472 rfi 473#endif /* !MINIMAL_SPL */ 474 475/* 476 * This code initialises the E300 processor core 477 * (conforms to PowerPC 603e spec) 478 * Note: expects original MSR contents to be in r5. 479 */ 480 .globl init_e300_core 481init_e300_core: /* time t 10 */ 482 /* Initialize machine status; enable machine check interrupt */ 483 /*-----------------------------------------------------------*/ 484 485 li r3, MSR_KERNEL /* Set ME and RI flags */ 486 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 487#ifdef DEBUG 488 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 489#endif 490 SYNC /* Some chip revs need this... */ 491 mtmsr r3 492 SYNC 493 mtspr SRR1, r3 /* Make SRR1 match MSR */ 494 495 496 lis r3, CONFIG_SYS_IMMR@h 497#if defined(CONFIG_WATCHDOG) 498 /* Initialise the Watchdog values and reset it (if req) */ 499 /*------------------------------------------------------*/ 500 lis r4, CONFIG_SYS_WATCHDOG_VALUE 501 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 502 stw r4, SWCRR(r3) 503 504 /* and reset it */ 505 506 li r4, 0x556C 507 sth r4, SWSRR@l(r3) 508 li r4, -0x55C7 509 sth r4, SWSRR@l(r3) 510#else 511 /* Disable Watchdog */ 512 /*-------------------*/ 513 lwz r4, SWCRR(r3) 514 /* Check to see if its enabled for disabling 515 once disabled by SW you can't re-enable */ 516 andi. r4, r4, 0x4 517 beq 1f 518 xor r4, r4, r4 519 stw r4, SWCRR(r3) 5201: 521#endif /* CONFIG_WATCHDOG */ 522 523#if defined(CONFIG_MASK_AER_AO) 524 /* Write the Arbiter Event Enable to mask Address Only traps. */ 525 /* This prevents the dcbz instruction from being trapped when */ 526 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 527 /* COHERENCY bit is set in the WIMG bits, which is often */ 528 /* needed for PCI operation. */ 529 lwz r4, 0x0808(r3) 530 rlwinm r0, r4, 0, ~AER_AO 531 stw r0, 0x0808(r3) 532#endif /* CONFIG_MASK_AER_AO */ 533 534 /* Initialize the Hardware Implementation-dependent Registers */ 535 /* HID0 also contains cache control */ 536 /* - force invalidation of data and instruction caches */ 537 /*------------------------------------------------------*/ 538 539 lis r3, CONFIG_SYS_HID0_INIT@h 540 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 541 SYNC 542 mtspr HID0, r3 543 544 lis r3, CONFIG_SYS_HID0_FINAL@h 545 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 546 SYNC 547 mtspr HID0, r3 548 549 lis r3, CONFIG_SYS_HID2@h 550 ori r3, r3, CONFIG_SYS_HID2@l 551 SYNC 552 mtspr HID2, r3 553 554 /* Done! */ 555 /*------------------------------*/ 556 blr 557 558 /* setup_bats - set them up to some initial state */ 559 .globl setup_bats 560setup_bats: 561 addis r0, r0, 0x0000 562 563 /* IBAT 0 */ 564 addis r4, r0, CONFIG_SYS_IBAT0L@h 565 ori r4, r4, CONFIG_SYS_IBAT0L@l 566 addis r3, r0, CONFIG_SYS_IBAT0U@h 567 ori r3, r3, CONFIG_SYS_IBAT0U@l 568 mtspr IBAT0L, r4 569 mtspr IBAT0U, r3 570 571 /* DBAT 0 */ 572 addis r4, r0, CONFIG_SYS_DBAT0L@h 573 ori r4, r4, CONFIG_SYS_DBAT0L@l 574 addis r3, r0, CONFIG_SYS_DBAT0U@h 575 ori r3, r3, CONFIG_SYS_DBAT0U@l 576 mtspr DBAT0L, r4 577 mtspr DBAT0U, r3 578 579 /* IBAT 1 */ 580 addis r4, r0, CONFIG_SYS_IBAT1L@h 581 ori r4, r4, CONFIG_SYS_IBAT1L@l 582 addis r3, r0, CONFIG_SYS_IBAT1U@h 583 ori r3, r3, CONFIG_SYS_IBAT1U@l 584 mtspr IBAT1L, r4 585 mtspr IBAT1U, r3 586 587 /* DBAT 1 */ 588 addis r4, r0, CONFIG_SYS_DBAT1L@h 589 ori r4, r4, CONFIG_SYS_DBAT1L@l 590 addis r3, r0, CONFIG_SYS_DBAT1U@h 591 ori r3, r3, CONFIG_SYS_DBAT1U@l 592 mtspr DBAT1L, r4 593 mtspr DBAT1U, r3 594 595 /* IBAT 2 */ 596 addis r4, r0, CONFIG_SYS_IBAT2L@h 597 ori r4, r4, CONFIG_SYS_IBAT2L@l 598 addis r3, r0, CONFIG_SYS_IBAT2U@h 599 ori r3, r3, CONFIG_SYS_IBAT2U@l 600 mtspr IBAT2L, r4 601 mtspr IBAT2U, r3 602 603 /* DBAT 2 */ 604 addis r4, r0, CONFIG_SYS_DBAT2L@h 605 ori r4, r4, CONFIG_SYS_DBAT2L@l 606 addis r3, r0, CONFIG_SYS_DBAT2U@h 607 ori r3, r3, CONFIG_SYS_DBAT2U@l 608 mtspr DBAT2L, r4 609 mtspr DBAT2U, r3 610 611 /* IBAT 3 */ 612 addis r4, r0, CONFIG_SYS_IBAT3L@h 613 ori r4, r4, CONFIG_SYS_IBAT3L@l 614 addis r3, r0, CONFIG_SYS_IBAT3U@h 615 ori r3, r3, CONFIG_SYS_IBAT3U@l 616 mtspr IBAT3L, r4 617 mtspr IBAT3U, r3 618 619 /* DBAT 3 */ 620 addis r4, r0, CONFIG_SYS_DBAT3L@h 621 ori r4, r4, CONFIG_SYS_DBAT3L@l 622 addis r3, r0, CONFIG_SYS_DBAT3U@h 623 ori r3, r3, CONFIG_SYS_DBAT3U@l 624 mtspr DBAT3L, r4 625 mtspr DBAT3U, r3 626 627#ifdef CONFIG_HIGH_BATS 628 /* IBAT 4 */ 629 addis r4, r0, CONFIG_SYS_IBAT4L@h 630 ori r4, r4, CONFIG_SYS_IBAT4L@l 631 addis r3, r0, CONFIG_SYS_IBAT4U@h 632 ori r3, r3, CONFIG_SYS_IBAT4U@l 633 mtspr IBAT4L, r4 634 mtspr IBAT4U, r3 635 636 /* DBAT 4 */ 637 addis r4, r0, CONFIG_SYS_DBAT4L@h 638 ori r4, r4, CONFIG_SYS_DBAT4L@l 639 addis r3, r0, CONFIG_SYS_DBAT4U@h 640 ori r3, r3, CONFIG_SYS_DBAT4U@l 641 mtspr DBAT4L, r4 642 mtspr DBAT4U, r3 643 644 /* IBAT 5 */ 645 addis r4, r0, CONFIG_SYS_IBAT5L@h 646 ori r4, r4, CONFIG_SYS_IBAT5L@l 647 addis r3, r0, CONFIG_SYS_IBAT5U@h 648 ori r3, r3, CONFIG_SYS_IBAT5U@l 649 mtspr IBAT5L, r4 650 mtspr IBAT5U, r3 651 652 /* DBAT 5 */ 653 addis r4, r0, CONFIG_SYS_DBAT5L@h 654 ori r4, r4, CONFIG_SYS_DBAT5L@l 655 addis r3, r0, CONFIG_SYS_DBAT5U@h 656 ori r3, r3, CONFIG_SYS_DBAT5U@l 657 mtspr DBAT5L, r4 658 mtspr DBAT5U, r3 659 660 /* IBAT 6 */ 661 addis r4, r0, CONFIG_SYS_IBAT6L@h 662 ori r4, r4, CONFIG_SYS_IBAT6L@l 663 addis r3, r0, CONFIG_SYS_IBAT6U@h 664 ori r3, r3, CONFIG_SYS_IBAT6U@l 665 mtspr IBAT6L, r4 666 mtspr IBAT6U, r3 667 668 /* DBAT 6 */ 669 addis r4, r0, CONFIG_SYS_DBAT6L@h 670 ori r4, r4, CONFIG_SYS_DBAT6L@l 671 addis r3, r0, CONFIG_SYS_DBAT6U@h 672 ori r3, r3, CONFIG_SYS_DBAT6U@l 673 mtspr DBAT6L, r4 674 mtspr DBAT6U, r3 675 676 /* IBAT 7 */ 677 addis r4, r0, CONFIG_SYS_IBAT7L@h 678 ori r4, r4, CONFIG_SYS_IBAT7L@l 679 addis r3, r0, CONFIG_SYS_IBAT7U@h 680 ori r3, r3, CONFIG_SYS_IBAT7U@l 681 mtspr IBAT7L, r4 682 mtspr IBAT7U, r3 683 684 /* DBAT 7 */ 685 addis r4, r0, CONFIG_SYS_DBAT7L@h 686 ori r4, r4, CONFIG_SYS_DBAT7L@l 687 addis r3, r0, CONFIG_SYS_DBAT7U@h 688 ori r3, r3, CONFIG_SYS_DBAT7U@l 689 mtspr DBAT7L, r4 690 mtspr DBAT7U, r3 691#endif 692 693 isync 694 695 /* invalidate all tlb's 696 * 697 * From the 603e User Manual: "The 603e provides the ability to 698 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 699 * instruction invalidates the TLB entry indexed by the EA, and 700 * operates on both the instruction and data TLBs simultaneously 701 * invalidating four TLB entries (both sets in each TLB). The 702 * index corresponds to bits 15-19 of the EA. To invalidate all 703 * entries within both TLBs, 32 tlbie instructions should be 704 * issued, incrementing this field by one each time." 705 * 706 * "Note that the tlbia instruction is not implemented on the 707 * 603e." 708 * 709 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 710 * incrementing by 0x1000 each time. The code below is sort of 711 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 712 * 713 */ 714 lis r3, 0 715 lis r5, 2 716 7171: 718 tlbie r3 719 addi r3, r3, 0x1000 720 cmp 0, 0, r3, r5 721 blt 1b 722 723 blr 724 725/* Cache functions. 726 * 727 * Note: requires that all cache bits in 728 * HID0 are in the low half word. 729 */ 730#ifndef MINIMAL_SPL 731 .globl icache_enable 732icache_enable: 733 mfspr r3, HID0 734 ori r3, r3, HID0_ICE 735 li r4, HID0_ICFI|HID0_ILOCK 736 andc r3, r3, r4 737 ori r4, r3, HID0_ICFI 738 isync 739 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 740 isync 741 mtspr HID0, r3 /* clears invalidate */ 742 blr 743 744 .globl icache_disable 745icache_disable: 746 mfspr r3, HID0 747 lis r4, 0 748 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 749 andc r3, r3, r4 750 isync 751 mtspr HID0, r3 /* clears invalidate, enable and lock */ 752 blr 753 754 .globl icache_status 755icache_status: 756 mfspr r3, HID0 757 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 758 blr 759#endif /* !MINIMAL_SPL */ 760 761 .globl dcache_enable 762dcache_enable: 763 mfspr r3, HID0 764 li r5, HID0_DCFI|HID0_DLOCK 765 andc r3, r3, r5 766 ori r3, r3, HID0_DCE 767 sync 768 mtspr HID0, r3 /* enable, no invalidate */ 769 blr 770 771 .globl dcache_disable 772dcache_disable: 773 mflr r4 774 bl flush_dcache /* uses r3 and r5 */ 775 mfspr r3, HID0 776 li r5, HID0_DCE|HID0_DLOCK 777 andc r3, r3, r5 778 ori r5, r3, HID0_DCFI 779 sync 780 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 781 sync 782 mtspr HID0, r3 /* clears invalidate */ 783 mtlr r4 784 blr 785 786 .globl dcache_status 787dcache_status: 788 mfspr r3, HID0 789 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 790 blr 791 792 .globl flush_dcache 793flush_dcache: 794 lis r3, 0 795 lis r5, CONFIG_SYS_CACHELINE_SIZE 7961: cmp 0, 1, r3, r5 797 bge 2f 798 lwz r5, 0(r3) 799 lis r5, CONFIG_SYS_CACHELINE_SIZE 800 addi r3, r3, 0x4 801 b 1b 8022: blr 803 804/*-------------------------------------------------------------------*/ 805 806/* 807 * void relocate_code(addr_sp, gd, addr_moni) 808 * 809 * This "function" does not return, instead it continues in RAM 810 * after relocating the monitor code. 811 * 812 * r3 = dest 813 * r4 = src 814 * r5 = length in bytes 815 * r6 = cachelinesize 816 */ 817 .globl relocate_code 818relocate_code: 819 mr r1, r3 /* Set new stack pointer */ 820 mr r9, r4 /* Save copy of Global Data pointer */ 821 mr r10, r5 /* Save copy of Destination Address */ 822 823 GET_GOT 824 mr r3, r5 /* Destination Address */ 825 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 826 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 827 lwz r5, GOT(__bss_start) 828 sub r5, r5, r4 829 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 830 831 /* 832 * Fix GOT pointer: 833 * 834 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 835 * + Destination Address 836 * 837 * Offset: 838 */ 839 sub r15, r10, r4 840 841 /* First our own GOT */ 842 add r12, r12, r15 843 /* then the one used by the C code */ 844 add r30, r30, r15 845 846 /* 847 * Now relocate code 848 */ 849 850 cmplw cr1,r3,r4 851 addi r0,r5,3 852 srwi. r0,r0,2 853 beq cr1,4f /* In place copy is not necessary */ 854 beq 7f /* Protect against 0 count */ 855 mtctr r0 856 bge cr1,2f 857 la r8,-4(r4) 858 la r7,-4(r3) 859 860 /* copy */ 8611: lwzu r0,4(r8) 862 stwu r0,4(r7) 863 bdnz 1b 864 865 addi r0,r5,3 866 srwi. r0,r0,2 867 mtctr r0 868 la r8,-4(r4) 869 la r7,-4(r3) 870 871 /* and compare */ 87220: lwzu r20,4(r8) 873 lwzu r21,4(r7) 874 xor. r22, r20, r21 875 bne 30f 876 bdnz 20b 877 b 4f 878 879 /* compare failed */ 88030: li r3, 0 881 blr 882 8832: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 884 add r8,r4,r0 885 add r7,r3,r0 8863: lwzu r0,-4(r8) 887 stwu r0,-4(r7) 888 bdnz 3b 889 890/* 891 * Now flush the cache: note that we must start from a cache aligned 892 * address. Otherwise we might miss one cache line. 893 */ 8944: cmpwi r6,0 895 add r5,r3,r5 896 beq 7f /* Always flush prefetch queue in any case */ 897 subi r0,r6,1 898 andc r3,r3,r0 899 mr r4,r3 9005: dcbst 0,r4 901 add r4,r4,r6 902 cmplw r4,r5 903 blt 5b 904 sync /* Wait for all dcbst to complete on bus */ 905 mr r4,r3 9066: icbi 0,r4 907 add r4,r4,r6 908 cmplw r4,r5 909 blt 6b 9107: sync /* Wait for all icbi to complete on bus */ 911 isync 912 913/* 914 * We are done. Do not return, instead branch to second part of board 915 * initialization, now running from RAM. 916 */ 917 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 918 mtlr r0 919 blr 920 921in_ram: 922 923 /* 924 * Relocation Function, r12 point to got2+0x8000 925 * 926 * Adjust got2 pointers, no need to check for 0, this code 927 * already puts a few entries in the table. 928 */ 929 li r0,__got2_entries@sectoff@l 930 la r3,GOT(_GOT2_TABLE_) 931 lwz r11,GOT(_GOT2_TABLE_) 932 mtctr r0 933 sub r11,r3,r11 934 addi r3,r3,-4 9351: lwzu r0,4(r3) 936 cmpwi r0,0 937 beq- 2f 938 add r0,r0,r11 939 stw r0,0(r3) 9402: bdnz 1b 941 942#ifndef MINIMAL_SPL 943 /* 944 * Now adjust the fixups and the pointers to the fixups 945 * in case we need to move ourselves again. 946 */ 947 li r0,__fixup_entries@sectoff@l 948 lwz r3,GOT(_FIXUP_TABLE_) 949 cmpwi r0,0 950 mtctr r0 951 addi r3,r3,-4 952 beq 4f 9533: lwzu r4,4(r3) 954 lwzux r0,r4,r11 955 cmpwi r0,0 956 add r0,r0,r11 957 stw r4,0(r3) 958 beq- 5f 959 stw r0,0(r4) 9605: bdnz 3b 9614: 962#endif 963 964clear_bss: 965 /* 966 * Now clear BSS segment 967 */ 968 lwz r3,GOT(__bss_start) 969 lwz r4,GOT(__bss_end) 970 971 cmplw 0, r3, r4 972 beq 6f 973 974 li r0, 0 9755: 976 stw r0, 0(r3) 977 addi r3, r3, 4 978 cmplw 0, r3, r4 979 bne 5b 9806: 981 982 mr r3, r9 /* Global Data pointer */ 983 mr r4, r10 /* Destination Address */ 984 bl board_init_r 985 986#ifndef MINIMAL_SPL 987 /* 988 * Copy exception vector code to low memory 989 * 990 * r3: dest_addr 991 * r7: source address, r8: end address, r9: target address 992 */ 993 .globl trap_init 994trap_init: 995 mflr r4 /* save link register */ 996 GET_GOT 997 lwz r7, GOT(_start) 998 lwz r8, GOT(_end_of_vectors) 999 1000 li r9, 0x100 /* reset vector always at 0x100 */ 1001 1002 cmplw 0, r7, r8 1003 bgelr /* return if r7>=r8 - just in case */ 10041: 1005 lwz r0, 0(r7) 1006 stw r0, 0(r9) 1007 addi r7, r7, 4 1008 addi r9, r9, 4 1009 cmplw 0, r7, r8 1010 bne 1b 1011 1012 /* 1013 * relocate `hdlr' and `int_return' entries 1014 */ 1015 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1016 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10172: 1018 bl trap_reloc 1019 addi r7, r7, 0x100 /* next exception vector */ 1020 cmplw 0, r7, r8 1021 blt 2b 1022 1023 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1024 bl trap_reloc 1025 1026 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1027 bl trap_reloc 1028 1029 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1030 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10313: 1032 bl trap_reloc 1033 addi r7, r7, 0x100 /* next exception vector */ 1034 cmplw 0, r7, r8 1035 blt 3b 1036 1037 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1038 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10394: 1040 bl trap_reloc 1041 addi r7, r7, 0x100 /* next exception vector */ 1042 cmplw 0, r7, r8 1043 blt 4b 1044 1045 mfmsr r3 /* now that the vectors have */ 1046 lis r7, MSR_IP@h /* relocated into low memory */ 1047 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1048 andc r3, r3, r7 /* (if it was on) */ 1049 SYNC /* Some chip revs need this... */ 1050 mtmsr r3 1051 SYNC 1052 1053 mtlr r4 /* restore link register */ 1054 blr 1055 1056#endif /* !MINIMAL_SPL */ 1057 1058#ifdef CONFIG_SYS_INIT_RAM_LOCK 1059lock_ram_in_cache: 1060 /* Allocate Initial RAM in data cache. 1061 */ 1062 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1063 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1064 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1065 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1066 mtctr r4 10671: 1068 dcbz r0, r3 1069 addi r3, r3, 32 1070 bdnz 1b 1071 1072 /* Lock the data cache */ 1073 mfspr r0, HID0 1074 ori r0, r0, HID0_DLOCK 1075 sync 1076 mtspr HID0, r0 1077 sync 1078 blr 1079 1080#ifndef MINIMAL_SPL 1081.globl unlock_ram_in_cache 1082unlock_ram_in_cache: 1083 /* invalidate the INIT_RAM section */ 1084 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1085 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1086 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1087 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1088 mtctr r4 10891: icbi r0, r3 1090 dcbi r0, r3 1091 addi r3, r3, 32 1092 bdnz 1b 1093 sync /* Wait for all icbi to complete on bus */ 1094 isync 1095 1096 /* Unlock the data cache and invalidate it */ 1097 mfspr r3, HID0 1098 li r5, HID0_DLOCK|HID0_DCFI 1099 andc r3, r3, r5 /* no invalidate, unlock */ 1100 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1101 sync 1102 mtspr HID0, r5 /* invalidate, unlock */ 1103 sync 1104 mtspr HID0, r3 /* no invalidate, unlock */ 1105 blr 1106#endif /* !MINIMAL_SPL */ 1107#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1108 1109#ifdef CONFIG_SYS_FLASHBOOT 1110map_flash_by_law1: 1111 /* When booting from ROM (Flash or EPROM), clear the */ 1112 /* Address Mask in OR0 so ROM appears everywhere */ 1113 /*----------------------------------------------------*/ 1114 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1115 lwz r4, OR0@l(r3) 1116 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1117 and r4, r4, r5 1118 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1119 1120 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1121 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1122 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1123 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1124 * 0xFF800. From the hard resetting to here, the processor fetched and 1125 * executed the instructions one by one. There is not absolutely 1126 * jumping happened. Laterly, the u-boot code has to do an absolutely 1127 * jumping to tell the CPU instruction fetching component what the 1128 * u-boot TEXT base address is. Because the TEXT base resides in the 1129 * boot ROM memory space, to garantee the code can run smoothly after 1130 * that jumping, we must map in the entire boot ROM by Local Access 1131 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1132 * address for boot ROM, such as 0xFE000000. In this case, the default 1133 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1134 * need another window to map in it. 1135 */ 1136 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1137 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1138 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1139 1140 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1141 lis r4, (0x80000012)@h 1142 ori r4, r4, (0x80000012)@l 1143 li r5, CONFIG_SYS_FLASH_SIZE 11441: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1145 addi r4, r4, 1 1146 bne 1b 1147 1148 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1149 /* Wait for HW to catch up */ 1150 lwz r4, LBLAWAR1(r3) 1151 twi 0,r4,0 1152 isync 1153 blr 1154 1155 /* Though all the LBIU Local Access Windows and LBC Banks will be 1156 * initialized in the C code, we'd better configure boot ROM's 1157 * window 0 and bank 0 correctly at here. 1158 */ 1159remap_flash_by_law0: 1160 /* Initialize the BR0 with the boot ROM starting address. */ 1161 lwz r4, BR0(r3) 1162 li r5, 0x7FFF 1163 and r4, r4, r5 1164 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1165 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1166 or r5, r5, r4 1167 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1168 1169 lwz r4, OR0(r3) 1170 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1171 or r4, r4, r5 1172 stw r4, OR0(r3) 1173 1174 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1175 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1176 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1177 1178 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1179 lis r4, (0x80000012)@h 1180 ori r4, r4, (0x80000012)@l 1181 li r5, CONFIG_SYS_FLASH_SIZE 11821: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1183 addi r4, r4, 1 1184 bne 1b 1185 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1186 1187 1188 xor r4, r4, r4 1189 stw r4, LBLAWBAR1(r3) 1190 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1191 /* Wait for HW to catch up */ 1192 lwz r4, LBLAWAR1(r3) 1193 twi 0,r4,0 1194 isync 1195 blr 1196#endif /* CONFIG_SYS_FLASHBOOT */ 1197