1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <init.h>
9 #include <linux/compiler.h>
10 #include <fsl_errata.h>
11 #include <asm/processor.h>
12 #include <fsl_usb.h>
13 #include "fsl_corenet_serdes.h"
14
15 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
16 /*
17 * This work-around is implemented in PBI, so just check to see if the
18 * work-around was actually applied. To do this, we check for specific data
19 * at specific addresses in DCSR.
20 *
21 * Array offsets[] contains a list of offsets within DCSR. According to the
22 * erratum document, the value at each offset should be 2.
23 */
check_erratum_a4849(uint32_t svr)24 static void check_erratum_a4849(uint32_t svr)
25 {
26 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
27 unsigned int i;
28
29 #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
30 static const uint8_t offsets[] = {
31 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
32 };
33 #endif
34 #ifdef CONFIG_ARCH_P4080
35 static const uint8_t offsets[] = {
36 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
37 };
38 #endif
39 uint32_t x108; /* The value that should be at offset 0x108 */
40
41 for (i = 0; i < ARRAY_SIZE(offsets); i++) {
42 if (in_be32(dcsr + offsets[i]) != 2) {
43 printf("Work-around for Erratum A004849 is not enabled\n");
44 return;
45 }
46 }
47
48 #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
49 x108 = 0x12;
50 #endif
51
52 #ifdef CONFIG_ARCH_P4080
53 /*
54 * For P4080, the erratum document says that the value at offset 0x108
55 * should be 0x12 on rev2, or 0x1c on rev3.
56 */
57 if (SVR_MAJ(svr) == 2)
58 x108 = 0x12;
59 if (SVR_MAJ(svr) == 3)
60 x108 = 0x1c;
61 #endif
62
63 if (in_be32(dcsr + 0x108) != x108) {
64 printf("Work-around for Erratum A004849 is not enabled\n");
65 return;
66 }
67
68 /* Everything matches, so the erratum work-around was applied */
69
70 printf("Work-around for Erratum A004849 enabled\n");
71 }
72 #endif
73
74 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
75 /*
76 * This work-around is implemented in PBI, so just check to see if the
77 * work-around was actually applied. To do this, we check for specific data
78 * at specific addresses in the SerDes register block.
79 *
80 * The work-around says that for each SerDes lane, write BnTTLCRy0 =
81 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
82
83 */
check_erratum_a4580(uint32_t svr)84 static void check_erratum_a4580(uint32_t svr)
85 {
86 const serdes_corenet_t __iomem *srds_regs =
87 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
88 unsigned int lane;
89
90 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
91 if (serdes_lane_enabled(lane)) {
92 const struct serdes_lane __iomem *srds_lane =
93 &srds_regs->lane[serdes_get_lane_idx(lane)];
94
95 /*
96 * Verify that the values we were supposed to write in
97 * the PBI are actually there. Also, the lower 15
98 * bits of res4[3] should be the same as the upper 15
99 * bits of res4[1].
100 */
101 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
102 (in_be32(&srds_lane->res4[1]) != 0x880000) ||
103 (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
104 printf("Work-around for Erratum A004580 is "
105 "not enabled\n");
106 return;
107 }
108 }
109 }
110
111 /* Everything matches, so the erratum work-around was applied */
112
113 printf("Work-around for Erratum A004580 enabled\n");
114 }
115 #endif
116
117 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
118 /*
119 * This workaround can be implemented in PBI, or by u-boot.
120 */
check_erratum_a007212(void)121 static void check_erratum_a007212(void)
122 {
123 u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
124
125 if (in_be32(plldgdcr) & 0x1fe) {
126 /* check if PLL ratio is set by workaround */
127 puts("Work-around for Erratum A007212 enabled\n");
128 }
129 }
130 #endif
131
do_errata(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])132 static int do_errata(struct cmd_tbl *cmdtp, int flag, int argc,
133 char *const argv[])
134 {
135 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
136 extern int enable_cpu_a011_workaround;
137 #endif
138 __maybe_unused u32 svr = get_svr();
139
140 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
141 if (IS_SVR_REV(svr, 1, 0)) {
142 switch (SVR_SOC_VER(svr)) {
143 case SVR_P1013:
144 case SVR_P1022:
145 puts("Work-around for Erratum SATA A001 enabled\n");
146 }
147 }
148 #endif
149
150 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
151 puts("Work-around for Erratum SERDES8 enabled\n");
152 #endif
153 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
154 puts("Work-around for Erratum SERDES9 enabled\n");
155 #endif
156 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
157 puts("Work-around for Erratum SERDES-A005 enabled\n");
158 #endif
159 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
160 if (SVR_MAJ(svr) < 3)
161 puts("Work-around for Erratum CPU22 enabled\n");
162 #endif
163 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
164 /*
165 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
166 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
167 * The SVR has been checked by cpu_init_r().
168 */
169 if (enable_cpu_a011_workaround)
170 puts("Work-around for Erratum CPU-A011 enabled\n");
171 #endif
172 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
173 puts("Work-around for Erratum CPU-A003999 enabled\n");
174 #endif
175 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
176 puts("Work-around for Erratum DDR-A003474 enabled\n");
177 #endif
178 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
179 puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
180 #endif
181 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
182 puts("Work-around for Erratum ESDHC111 enabled\n");
183 #endif
184 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
185 puts("Work-around for Erratum A004468 enabled\n");
186 #endif
187 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
188 puts("Work-around for Erratum ESDHC135 enabled\n");
189 #endif
190 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
191 if (SVR_MAJ(svr) < 3)
192 puts("Work-around for Erratum ESDHC13 enabled\n");
193 #endif
194 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
195 puts("Work-around for Erratum ESDHC-A001 enabled\n");
196 #endif
197 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
198 puts("Work-around for Erratum CPC-A002 enabled\n");
199 #endif
200 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
201 puts("Work-around for Erratum CPC-A003 enabled\n");
202 #endif
203 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
204 puts("Work-around for Erratum ELBC-A001 enabled\n");
205 #endif
206 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
207 puts("Work-around for Erratum DDR-A003 enabled\n");
208 #endif
209 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
210 puts("Work-around for Erratum DDR115 enabled\n");
211 #endif
212 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
213 puts("Work-around for Erratum DDR111 enabled\n");
214 puts("Work-around for Erratum DDR134 enabled\n");
215 #endif
216 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
217 puts("Work-around for Erratum IFC-A002769 enabled\n");
218 #endif
219 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
220 puts("Work-around for Erratum P1010-A003549 enabled\n");
221 #endif
222 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
223 puts("Work-around for Erratum IFC A-003399 enabled\n");
224 #endif
225 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
226 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
227 puts("Work-around for Erratum NMG DDR120 enabled\n");
228 #endif
229 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
230 puts("Work-around for Erratum NMG_LBC103 enabled\n");
231 #endif
232 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
233 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
234 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
235 #endif
236 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
237 puts("Work-around for Erratum A004508 enabled\n");
238 #endif
239 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
240 puts("Work-around for Erratum A004510 enabled\n");
241 #endif
242 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
243 puts("Work-around for Erratum SRIO-A004034 enabled\n");
244 #endif
245 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
246 puts("Work-around for Erratum A004934 enabled\n");
247 #endif
248 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
249 if (IS_SVR_REV(svr, 1, 0))
250 puts("Work-around for Erratum A005871 enabled\n");
251 #endif
252 #ifdef CONFIG_SYS_FSL_ERRATUM_A006475
253 if (SVR_MAJ(get_svr()) == 1)
254 puts("Work-around for Erratum A006475 enabled\n");
255 #endif
256 #ifdef CONFIG_SYS_FSL_ERRATUM_A006384
257 if (SVR_MAJ(get_svr()) == 1)
258 puts("Work-around for Erratum A006384 enabled\n");
259 #endif
260 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
261 /* This work-around is implemented in PBI, so just check for it */
262 check_erratum_a4849(svr);
263 #endif
264 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
265 /* This work-around is implemented in PBI, so just check for it */
266 check_erratum_a4580(svr);
267 #endif
268 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
269 puts("Work-around for Erratum PCIe-A003 enabled\n");
270 #endif
271 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
272 puts("Work-around for Erratum USB14 enabled\n");
273 #endif
274 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
275 if (has_erratum_a007186())
276 puts("Work-around for Erratum A007186 enabled\n");
277 #endif
278 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
279 puts("Work-around for Erratum A006593 enabled\n");
280 #endif
281 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
282 if (has_erratum_a006379())
283 puts("Work-around for Erratum A006379 enabled\n");
284 #endif
285 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
286 if (IS_SVR_REV(svr, 1, 0))
287 puts("Work-around for Erratum A003571 enabled\n");
288 #endif
289 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
290 puts("Work-around for Erratum A-005812 enabled\n");
291 #endif
292 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
293 puts("Work-around for Erratum A005125 enabled\n");
294 #endif
295 #ifdef CONFIG_SYS_FSL_ERRATUM_A007075
296 if (has_erratum_a007075())
297 puts("Work-around for Erratum A007075 enabled\n");
298 #endif
299 #ifdef CONFIG_SYS_FSL_ERRATUM_A007798
300 if (has_erratum_a007798())
301 puts("Work-around for Erratum A007798 enabled\n");
302 #endif
303 #ifdef CONFIG_SYS_FSL_ERRATUM_A004477
304 if (has_erratum_a004477())
305 puts("Work-around for Erratum A004477 enabled\n");
306 #endif
307 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
308 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
309 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
310 puts("Work-around for Erratum I2C-A004447 enabled\n");
311 #endif
312 #ifdef CONFIG_SYS_FSL_ERRATUM_A005275
313 if (has_erratum_a005275())
314 puts("Work-around for Erratum A005275 enabled\n");
315 #endif
316 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
317 if (has_erratum_a006261())
318 puts("Work-around for Erratum A006261 enabled\n");
319 #endif
320 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
321 check_erratum_a007212();
322 #endif
323 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
324 puts("Work-around for Erratum A-005434 enabled\n");
325 #endif
326 #if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
327 defined(CONFIG_A008044_WORKAROUND)
328 if (IS_SVR_REV(svr, 1, 0))
329 puts("Work-around for Erratum A-008044 enabled\n");
330 #endif
331 #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \
332 (defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS))
333 puts("Work-around for Erratum XFI on B4860QDS enabled\n");
334 #endif
335 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
336 puts("Work-around for Erratum A009663 enabled\n");
337 #endif
338 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
339 puts("Work-around for Erratum A007907 enabled\n");
340 #endif
341 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
342 puts("Work-around for Erratum A007815 enabled\n");
343 #endif
344
345 return 0;
346 }
347
348 U_BOOT_CMD(
349 errata, 1, 0, do_errata,
350 "Report errata workarounds",
351 ""
352 );
353