1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2002 (440 port)
7 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
8 *
9 * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
10 * Xianghua Xiao (X.Xiao@motorola.com)
11 */
12
13 #include <common.h>
14 #include <irq_func.h>
15 #include <log.h>
16 #include <time.h>
17 #include <watchdog.h>
18 #include <command.h>
19 #include <asm/processor.h>
20 #include <asm/io.h>
21 #ifdef CONFIG_POST
22 #include <post.h>
23 #endif
24 #include <asm/ptrace.h>
25
interrupt_init_cpu(unsigned * decrementer_count)26 void interrupt_init_cpu(unsigned *decrementer_count)
27 {
28 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
29
30 #ifdef CONFIG_POST
31 /*
32 * The POST word is stored in the PIC's TFRR register which gets
33 * cleared when the PIC is reset. Save it off so we can restore it
34 * later.
35 */
36 ulong post_word = post_word_load();
37 #endif
38
39 out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
40 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
41 ;
42 out_be32(&pic->gcr, MPC85xx_PICGCR_M);
43 in_be32(&pic->gcr);
44
45 *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
46
47 /* PIE is same as DIE, dec interrupt enable */
48 mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
49
50 #ifdef CONFIG_INTERRUPTS
51 pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
52 debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
53
54 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
55 debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
56
57 pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
58 debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
59
60 #ifdef CONFIG_PCI1
61 pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
62 debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
63 #endif
64 #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
65 pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
66 debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
67 #endif
68 #ifdef CONFIG_PCIE1
69 pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
70 debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
71 #endif
72 #ifdef CONFIG_PCIE3
73 pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
74 debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
75 #endif
76
77 pic->ctpr=0; /* 40080 clear current task priority register */
78 #endif
79
80 #ifdef CONFIG_POST
81 post_word_store(post_word);
82 #endif
83 }
84
85 /* Install and free a interrupt handler. Not implemented yet. */
86
87 void
irq_install_handler(int vec,interrupt_handler_t * handler,void * arg)88 irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
89 {
90 return;
91 }
92
93 void
irq_free_handler(int vec)94 irq_free_handler(int vec)
95 {
96 return;
97 }
98
timer_interrupt_cpu(struct pt_regs * regs)99 void timer_interrupt_cpu(struct pt_regs *regs)
100 {
101 /* PIS is same as DIS, dec interrupt status */
102 mtspr(SPRN_TSR, TSR_PIS);
103 }
104
105 #if defined(CONFIG_CMD_IRQ)
106 /* irqinfo - print information about PCI devices,not implemented. */
do_irqinfo(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])107 int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
108 {
109 return 0;
110 }
111 #endif
112