1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 /*
8 * m8xx.c
9 *
10 * CPU specific code
11 *
12 * written or collected and sometimes rewritten by
13 * Magnus Damm <damm@bitsmart.com>
14 *
15 * minor modifications by
16 * Wolfgang Denk <wd@denx.de>
17 */
18
19 #include <common.h>
20 #include <cpu_func.h>
21 #include <net.h>
22 #include <time.h>
23 #include <vsprintf.h>
24 #include <watchdog.h>
25 #include <command.h>
26 #include <mpc8xx.h>
27 #include <netdev.h>
28 #include <asm/cache.h>
29 #include <asm/cpm_8xx.h>
30 #include <asm/global_data.h>
31 #include <linux/compiler.h>
32 #include <asm/io.h>
33
34 #if defined(CONFIG_OF_LIBFDT)
35 #include <linux/libfdt.h>
36 #include <fdt_support.h>
37 #endif
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 /* ------------------------------------------------------------------------- */
42 /* L1 i-cache */
43
checkicache(void)44 int checkicache(void)
45 {
46 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
47 memctl8xx_t __iomem *memctl = &immap->im_memctl;
48 u32 cacheon = rd_ic_cst() & IDC_ENABLED;
49 /* probe in flash memoryarea */
50 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
51 u32 m;
52 u32 lines = -1;
53
54 wr_ic_cst(IDC_UNALL);
55 wr_ic_cst(IDC_INVALL);
56 wr_ic_cst(IDC_DISABLE);
57 __asm__ volatile ("isync");
58
59 while (!((m = rd_ic_cst()) & IDC_CERR2)) {
60 wr_ic_adr(k);
61 wr_ic_cst(IDC_LDLCK);
62 __asm__ volatile ("isync");
63
64 lines++;
65 k += 0x10; /* the number of bytes in a cacheline */
66 }
67
68 wr_ic_cst(IDC_UNALL);
69 wr_ic_cst(IDC_INVALL);
70
71 if (cacheon)
72 wr_ic_cst(IDC_ENABLE);
73 else
74 wr_ic_cst(IDC_DISABLE);
75
76 __asm__ volatile ("isync");
77
78 return lines << 4;
79 };
80
81 /* ------------------------------------------------------------------------- */
82 /* L1 d-cache */
83 /* call with cache disabled */
84
checkdcache(void)85 static int checkdcache(void)
86 {
87 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
88 memctl8xx_t __iomem *memctl = &immap->im_memctl;
89 u32 cacheon = rd_dc_cst() & IDC_ENABLED;
90 /* probe in flash memoryarea */
91 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
92 u32 m;
93 u32 lines = -1;
94
95 wr_dc_cst(IDC_UNALL);
96 wr_dc_cst(IDC_INVALL);
97 wr_dc_cst(IDC_DISABLE);
98
99 while (!((m = rd_dc_cst()) & IDC_CERR2)) {
100 wr_dc_adr(k);
101 wr_dc_cst(IDC_LDLCK);
102 lines++;
103 k += 0x10; /* the number of bytes in a cacheline */
104 }
105
106 wr_dc_cst(IDC_UNALL);
107 wr_dc_cst(IDC_INVALL);
108
109 if (cacheon)
110 wr_dc_cst(IDC_ENABLE);
111 else
112 wr_dc_cst(IDC_DISABLE);
113
114 return lines << 4;
115 };
116
check_CPU(long clock,uint pvr,uint immr)117 static int check_CPU(long clock, uint pvr, uint immr)
118 {
119 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
120 uint k;
121 char buf[32];
122
123 /* the highest 16 bits should be 0x0050 for a 860 */
124
125 if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
126 return -1;
127
128 k = (immr << 16) |
129 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
130
131 /*
132 * Some boards use sockets so different CPUs can be used.
133 * We have to check chip version in run time.
134 */
135 switch (k) {
136 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
137 case 0x08010004: /* Rev. A.0 */
138 printf("MPC866xxxZPnnA");
139 break;
140 case 0x08000003: /* Rev. 0.3 */
141 printf("MPC866xxxZPnn");
142 break;
143 case 0x09000000: /* 870/875/880/885 */
144 puts("MPC885ZPnn");
145 break;
146
147 default:
148 printf("unknown MPC86x (0x%08x)", k);
149 break;
150 }
151
152 printf(" at %s MHz: ", strmhz(buf, clock));
153
154 print_size(checkicache(), " I-Cache ");
155 print_size(checkdcache(), " D-Cache");
156
157 /* do we have a FEC (860T/P or 852/859/866/885)? */
158
159 out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
160 if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
161 printf(" FEC present");
162
163 putc('\n');
164
165 return 0;
166 }
167
168 /* ------------------------------------------------------------------------- */
169
checkcpu(void)170 int checkcpu(void)
171 {
172 ulong clock = gd->cpu_clk;
173 uint immr = get_immr(); /* Return full IMMR contents */
174 uint pvr = get_pvr();
175
176 puts("CPU: ");
177
178 return check_CPU(clock, pvr, immr);
179 }
180
181 /* ------------------------------------------------------------------------- */
182
upmconfig(uint upm,uint * table,uint size)183 void upmconfig(uint upm, uint *table, uint size)
184 {
185 uint i;
186 uint addr = 0;
187 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
188 memctl8xx_t __iomem *memctl = &immap->im_memctl;
189
190 for (i = 0; i < size; i++) {
191 out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
192 out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
193 addr++;
194 }
195 }
196
197 /* ------------------------------------------------------------------------- */
198
do_reset(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])199 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
200 {
201 ulong msr, addr;
202
203 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
204
205 /* Checkstop Reset enable */
206 setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
207
208 /* Interrupts and MMU off */
209 __asm__ volatile ("mtspr 81, 0");
210 __asm__ volatile ("mfmsr %0" : "=r" (msr));
211
212 msr &= ~0x1030;
213 __asm__ volatile ("mtmsr %0" : : "r" (msr));
214
215 /*
216 * Trying to execute the next instruction at a non-existing address
217 * should cause a machine check, resulting in reset
218 */
219 #ifdef CONFIG_SYS_RESET_ADDRESS
220 addr = CONFIG_SYS_RESET_ADDRESS;
221 #else
222 /*
223 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
224 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
225 * Better pick an address known to be invalid on your system and assign
226 * it to CONFIG_SYS_RESET_ADDRESS.
227 * "(ulong)-1" used to be a good choice for many systems...
228 */
229 addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
230 #endif
231 ((void (*)(void)) addr)();
232 return 1;
233 }
234
235 /* ------------------------------------------------------------------------- */
236
237 /*
238 * Get timebase clock frequency (like cpu_clk in Hz)
239 *
240 * See sections 14.2 and 14.6 of the User's Manual
241 */
get_tbclk(void)242 unsigned long get_tbclk(void)
243 {
244 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
245 ulong oscclk, factor, pll;
246
247 if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
248 return gd->cpu_clk / 16;
249
250 pll = in_be32(&immap->im_clkrst.car_plprcr);
251
252 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
253
254 /*
255 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
256 * factor is calculated as follows:
257 *
258 * MFN
259 * MFI + -------
260 * MFD + 1
261 * factor = -----------------
262 * (PDF + 1) * 2^S
263 *
264 */
265 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
266 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
267
268 oscclk = gd->cpu_clk / factor;
269
270 if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
271 factor > 2)
272 return oscclk / 4;
273
274 return oscclk / 16;
275 }
276
277 /*
278 * Initializes on-chip ethernet controllers.
279 * to override, implement board_eth_init()
280 */
cpu_eth_init(struct bd_info * bis)281 int cpu_eth_init(struct bd_info *bis)
282 {
283 #if defined(CONFIG_MPC8XX_FEC)
284 fec_initialize(bis);
285 #endif
286 return 0;
287 }
288