1#include <dt-bindings/memory/mpc83xx-sdram.h>
2#include <dt-bindings/clk/mpc83xx-clk.h>
3
4/ {
5	aliases {
6		i2c0 = &IIC;
7		i2c1 = &IIC2;
8		i2c2 = "/fpga0bus/fpga0_iic_main";
9		i2c3 = "/fpga0bus/fpga0_iic_video0";
10		i2c4 = "/fpga0bus/fpga0_iic_video1";
11		i2c5 = "/fpga0bus/fpga0_iic_usb";
12		gdsys_soc0 = "/fpga0bus";
13		gdsys_soc1 = "/fpga1bus";
14		ioep0 = "/fpga0bus/fpga0_ep0";
15		ioep1 = "/fpga0bus/fpga1_ep0";
16	};
17
18	chosen {
19		stdout-path = &serial1;
20	};
21
22	cpus {
23		compatible = "cpu_bus";
24		u-boot,dm-pre-reloc;
25
26		PowerPC,8308@0 {
27			compatible = "fsl,mpc8308";
28			clocks = <&socclocks MPC83XX_CLK_CORE
29			          &socclocks MPC83XX_CLK_CSB>;
30			u-boot,dm-pre-reloc;
31		};
32	};
33
34	board {
35		compatible = "gdsys,sysinfo-gazerbeam";
36		csb = <&board_soc>;
37		serdes = <&SERDES>;
38		rxaui0 = <&RXAUI0_0>;
39		rxaui1 = <&RXAUI0_1>;
40		rxaui2 = <&RXAUI0_2>;
41		rxaui3 = <&RXAUI0_3>;
42		rxaui4 = <&RXAUI1_0>;
43		rxaui5 = <&RXAUI1_1>;
44		rxaui6 = <&RXAUI1_2>;
45		rxaui7 = <&RXAUI1_3>;
46		fpga0 = <&FPGA0>;
47		fpga1 = <&FPGA1>;
48		ioep0 = <&IOEP0>;
49		ioep1 = <&IOEP1>;
50
51		ver-gpios = <&PPCPCA 12 0
52			     &PPCPCA 13 0
53			     &PPCPCA 14 0
54			     &PPCPCA 15 0>;
55
56		/* MC2/SC-Board */
57		var-gpios-mc2 = <&GPIO_VB0 0 0    /* VAR-MC_SC */
58				 &GPIO_VB0 11 0>; /* VAR-CON */
59		/* MC4-Board */
60		var-gpios-mc4 = <&GPIO_VB1 0 0    /* VAR-MC_SC */
61				 &GPIO_VB1 11 0>; /* VAR-CON */
62
63		reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
64	};
65
66	socclocks: clocks {
67		compatible = "fsl,mpc8308-clk";
68		#clock-cells = <1>;
69		u-boot,dm-pre-reloc;
70	};
71
72	timer {
73		compatible = "fsl,mpc83xx-timer";
74		clocks = <&socclocks MPC83XX_CLK_CSB>;
75	};
76};
77
78&FPGA0 {
79	reset-gpios = <&PPCPCA 26 0>;
80	done-gpios = <&GPIO_VB0 19 0>;
81};
82
83&FPGA1 {
84	status = "disable";
85};
86
87&FPGA0BUS {
88	ranges = <0x0 0xe0600000 0x00004000>;
89	fpga = <&FPGA0>;
90
91	fpga0_video0 {
92		mode = "640_480_60";
93
94		status = "disabled";
95	};
96
97	RXAUI0_0: fpga0_rxaui@fc0 {
98		compatible = "gdsys,rxaui_ctrl";
99		reg = <0x0fc0 0x10>;
100	};
101
102	fpga0_iic_video0  {
103		status = "disabled";
104	};
105
106	fpga0_axi_video0 {
107		status = "disabled";
108	};
109
110	fpga0_video1 {
111		mode = "640_480_60";
112		status = "disabled";
113	};
114
115	fpga0_iic_video1  {
116		status = "disabled";
117	};
118
119	fpga0_axi_video1 {
120		status = "disabled";
121	};
122
123	IOEP0: fpga0_ep0 {
124	};
125
126	RXAUI0_1: fpga0_rxaui@fd0 {
127		compatible = "gdsys,rxaui_ctrl";
128		reg = <0x0fd0 0x10>;
129	};
130
131	RXAUI0_2: fpga0_rxaui@fe0 {
132		compatible = "gdsys,rxaui_ctrl";
133		reg = <0x0fe0 0x10>;
134	};
135
136	RXAUI0_3: fpga0_rxaui@ff0 {
137		compatible = "gdsys,rxaui_ctrl";
138		reg = <0x0ff0 0x10>;
139	};
140};
141
142&FPGA1BUS {
143	ranges = <0x0 0xe0700000 0x00004000>;
144	fpga = <&FPGA1>;
145
146	status = "disable";
147
148	fpga1_video0 {
149		mode = "640_480_60";
150	};
151
152	RXAUI1_0: fpga0_rxaui@fc0 {
153		compatible = "gdsys,rxaui_ctrl";
154		reg = <0x0fc0 0x10>;
155	};
156
157	fpga1_video1 {
158		mode = "640_480_60";
159	};
160
161	IOEP1: fpga1_ep0 {
162	};
163
164	RXAUI1_1: fpga0_rxaui@fd0 {
165		compatible = "gdsys,rxaui_ctrl";
166		reg = <0x0fd0 0x10>;
167	};
168
169	RXAUI1_2: fpga0_rxaui@fe0 {
170		compatible = "gdsys,rxaui_ctrl";
171		reg = <0x0fe0 0x10>;
172	};
173
174	RXAUI1_3: fpga0_rxaui@ff0 {
175		compatible = "gdsys,rxaui_ctrl";
176		reg = <0x0ff0 0x10>;
177	};
178};
179
180&board_soc {
181	u-boot,dm-pre-reloc;
182	clocks = <&socclocks MPC83XX_CLK_CSB>;
183
184	memory@2000 {
185		u-boot,dm-pre-reloc;
186	};
187
188	sdhc@2e000 {
189		clocks = <&socclocks MPC83XX_CLK_SDHC>;
190		clock-names = "per";
191	};
192
193	SERDES: serdes@e3000 {
194		reg = <0xe3000 0x200>;
195		compatible = "fsl,mpc83xx-serdes";
196		proto = "pex";
197		serdes-clk = <100>;
198		vdd;
199	};
200};
201
202&IIC {
203	clocks = <&socclocks MPC83XX_CLK_I2C1>;
204
205	PPCPCA: pca9698@20 {
206		label = "ppc";
207	};
208
209	IOPCA: pca9698@22 {
210		label = "io";
211	};
212
213	at97sc3205t@29 {
214		u-boot,i2c-offset-len = <0>;
215	};
216};
217
218&IIC2 {
219	clocks = <&socclocks MPC83XX_CLK_I2C2>;
220
221	GPIO_VB0: pca9698@20 {
222		label = "mc2-sc";
223	};
224
225	GPIO_VB1: pca9698@22 {
226		label = "mc4";
227	};
228};
229
230&board_soc {
231	u-boot,dm-pre-reloc;
232};
233
234&GPIO_VB0 {
235	u-boot,dm-pre-reloc;
236};
237
238&serial0 {
239	clocks = <&socclocks MPC83XX_CLK_CSB>;
240	u-boot,dm-pre-reloc;
241};
242
243&serial1 {
244	clocks = <&socclocks MPC83XX_CLK_CSB>;
245	u-boot,dm-pre-reloc;
246};
247
248&pci0 {
249	clocks = <&socclocks MPC83XX_CLK_PCIEXP1>;
250};
251