1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Hitachi Power Grids KMCOGE5ne Device Tree Source 4 * 5 * Copyright (C) 2020 Heiko Schocher <hs@denx.de> 6 * 7 */ 8 9/dts-v1/; 10 11#include "km836x.dtsi" 12 13/ { 14 model = "kmcoge5ne"; 15 compatible = "hitachi,kmcoge5ne"; 16 17 aliases { 18 ethernet0 = &enet_admin; 19 ethernet1 = &enet_mate; 20 ethernet2 = &enet_switch; 21 serial0 = &serial0; 22 }; 23}; 24 25&soc { 26 /* brg for hdlc clk */ 27 brg@0 { 28 compatible = "fsl,mpc-brg"; 29 brg-name = "brg16"; 30 brg-frequency = <20000000>; /* 20 MHz */ 31 pio-handle = <&pio_brg>; 32 }; 33}; 34 35&i2c0 { 36 mux@70 { 37 compatible = "nxp,pca9547"; 38 reg = <0x70>; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 i2c@1 { 43 reg = <1>; 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 /* Inventory EEPROM of the unit itself */ 48 ivm@50 { 49 label = "MAIN_CTRL"; 50 compatible = "dummy"; 51 reg = <0x50>; 52 }; 53 }; 54 55 i2c@2 { 56 reg = <2>; 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 /* Inventory EEPROM of the fan unit */ 61 fanu-ivm@50 { 62 label = "FANUV"; 63 compatible = "dummy"; 64 reg = <0x50>; 65 }; 66 67 /* fan unit (GPIOs and so on) */ 68 fanu@20 { 69 label = "FANUV_CTRL"; 70 compatible = "dummy"; 71 reg = <0x20>; 72 }; 73 }; 74 75 i2c@3 { 76 reg = <3>; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 backplane@50 { 81 label = "BP_CTRL"; 82 compatible = "dummy"; 83 reg = <0x50>; 84 }; 85 }; 86 }; 87}; 88 89&serial0 { 90 status = "okay"; 91}; 92 93&par_io { 94 pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */ 95 pio-map = < 96 /* port pin dir open_drain assignment has_irq */ 97 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ 98 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ 99 100 0 3 1 0 1 0 /* TxD0 (PA3, in, f1) */ 101 0 4 1 0 1 0 /* TxD1 (PA4, in, f1) */ 102 0 5 1 0 1 0 /* TxD2 (PA5, in, f1) */ 103 0 6 1 0 1 0 /* TxD3 (PA6, in, f1) */ 104 0 9 2 0 1 0 /* RxD0 (PA9, out, f1) */ 105 0 10 2 0 1 0 /* RxD1 (PA10, out, f1) */ 106 0 11 2 0 1 0 /* RxD2 (PA11, out, f1) */ 107 0 12 2 0 1 0 /* RxD3 (PA12, out, f1) */ 108 0 7 1 0 1 0 /* TX_EN (PA7, in, f1) */ 109 0 15 2 0 1 0 /* RX_DV (PA15, out, f1) */ 110 0 0 2 0 1 0 /* RX_CLK (PA0, out, f1) */ 111 2 9 1 0 3 0 /* GTX_CLK (CLK10) */ 112 2 8 2 0 1 0 /* GTX125 (CLK9) */ 113 >; 114 }; 115 116 pio_ucc4: ucc_pin@3 { /* RMII, admin front port */ 117 pio-map = < 118 /* port pin dir open_drain assignment has_irq */ 119 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ 120 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ 121 122 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ 123 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ 124 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ 125 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ 126 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ 127 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ 128 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ 129 130 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ 131 >; 132 }; 133 134 pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */ 135 pio-map = < 136 /* port pin dir open_drain assignment has_irq */ 137 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ 138 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ 139 140 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ 141 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ 142 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ 143 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ 144 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ 145 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ 146 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ 147 148 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ 149 >; 150 }; 151 152 pio_spi: spi_pin@01 { 153 pio-map = < 154 /* port pin dir open_drain assignment has_irq */ 155 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3) */ 156 4 29 3 0 3 0 /* SPI_MISO (PE29, out, f3) */ 157 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3) */ 158 >; 159 }; 160 161 pio_brg: brg_pin@0 { 162 pio-map = < 163 /* port pin dir open_drain assignment has_irq */ 164 2 25 1 0 1 0 /* BRG (PC25, out, f1) */ 165 >; 166 }; 167 168 pio_tdm: tdm_pin@00 { 169 pio-map = < 170 /* port pin dir open_drain assignment has_irq */ 171 /* TDMa */ 172 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ 173 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ 174 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ 175 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ 176 /* TDMb */ 177 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ 178 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ 179 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ 180 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ 181 /* TDMc */ 182 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ 183 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ 184 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ 185 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ 186 /* TDMd */ 187 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ 188 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ 189 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ 190 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ 191 /* TDMe */ 192 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ 193 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ 194 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ 195 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ 196 /* TDMf */ 197 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ 198 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ 199 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ 200 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ 201 /* TDMg */ 202 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ 203 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ 204 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ 205 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ 206 /* TDMh */ 207 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ 208 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ 209 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ 210 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ 211 /* RxTxClk0/1 */ 212 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ 213 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ 214 /* RxTxSync0/1 */ 215 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ 216 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ 217 }; 218}; 219 220&qe { 221 /* mng-switch port (UCC1, MDIO 0x10, RGMII) */ 222 enet_switch: ethernet@2000 { 223 device_type = "network"; 224 compatible = "ucc_geth"; 225 cell-index = <1>; 226 reg = <0x2000 0x200>; 227 interrupts = <32>; 228 interrupt-parent = <&qeic>; 229 local-mac-address = [ 00 00 00 00 00 00 ]; 230 rx-clock-name = "none"; 231 tx-clock-name = "clk9"; 232 /*id=0, full-dup, 1G, no-pause, no-asym_p*/ 233 fixed-link = <0 1 1000 0 0>; 234 phy-connection-type = "rgmii-id"; 235 pio-handle = <&pio_ucc1>; 236 }; 237 238 /* admin and debug port (UCC4, MDIO 0x00, RMII) */ 239 enet_admin: ucc@3200 { 240 device_type = "network"; 241 compatible = "ucc_geth"; 242 cell-index = <4>; 243 reg = <0x3200 0x200>; 244 interrupts = <35>; 245 interrupt-parent = <&qeic>; 246 local-mac-address = [ 00 00 00 00 00 00 ]; 247 rx-clock-name = "none"; 248 tx-clock-name = "clk17"; 249 phy-handle = <&phy_admin>; 250 phy-connection-type = "rmii"; 251 pio-handle = <&pio_ucc4>; 252 }; 253 254 /* mate backplane port (UCC5, MDIO 0x08, RMII) */ 255 enet_mate: ucc@2400 { 256 device_type = "network"; 257 compatible = "ucc_geth"; 258 cell-index = <5>; 259 reg = <0x2400 0x200>; 260 interrupts = <40>; 261 interrupt-parent = <&qeic>; 262 local-mac-address = [ 00 00 00 00 00 00 ]; 263 rx-clock-name = "none"; 264 tx-clock-name = "clk16"; 265 phy-handle = <&phy_mate>; 266 phy-connection-type = "rmii"; 267 pio-handle = <&pio_ucc5>; 268 }; 269 270 mdio@3320 { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 reg = <0x3320 0x18>; 274 compatible = "fsl,ucc-mdio"; 275 276 /* admin front port (UCC4, MDIO 0x00, RMII) */ 277 phy_admin: ethernet-phy@00 { 278 reg = <0x0>; 279 }; 280 281 /* mate bp port (UCC5, MDIO 0x08, RMII) */ 282 phy_mate: ethernet-phy@08 { 283 reg = <0x08>; 284 }; 285 }; 286}; 287 288&localbus { 289 ranges = <0 0 0xf0000000 0x04000000 290 1 0 0xe8000000 0x01000000 291 3 0 0xa0000000 0x10000000 292 4 0 0xb0000000 0x10000000>; 293 294 flash@0,0 { 295 compatible = "cfi-flash"; 296 reg = <0 0 0x04000000>; 297 nornand = "nor"; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 bank-width = <2>; 301 partition@0 { /* 768KB */ 302 label = "u-boot"; 303 reg = <0 0xC0000>; 304 }; 305 partition@c0000 { /* 128KB */ 306 label = "env"; 307 reg = <0xC0000 0x20000>; 308 }; 309 partition@e0000 { /* 128KB */ 310 label = "envred"; 311 reg = <0xE0000 0x20000>; 312 }; 313 partition@100000 { /* 64512KB */ 314 label = "ubi0"; 315 reg = <0x100000 0x3F00000>; 316 }; 317 }; 318}; 319 320#include "kmcoge5ne-uboot.dtsi" 321