1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Hitachi Power Grids SUPM5 Device Tree Source
4 *
5 * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
6 *
7 */
8
9/dts-v1/;
10
11#include "km8321.dtsi"
12
13/ {
14	model = "SUPM5";
15	compatible = "hitachi,kmpbec8321";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet_piggy2;
21		serial0 = &serial0;
22	};
23};
24
25&i2c0 {
26	mux@70 {
27		compatible = "nxp,pca9547";
28		reg = <0x70>;
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		i2c@1 {
33			reg = <1>;
34			#address-cells = <1>;
35			#size-cells = <0>;
36
37			/* Inventory EEPROM of the unit itself */
38			ivm@50 {
39				label = "MAIN_CTRL";
40				compatible = "dummy";
41				reg = <0x50>;
42			};
43		};
44
45		i2c@2 {
46			reg = <2>;
47			#address-cells = <1>;
48			#size-cells = <0>;
49
50			/* Temperature sensors */
51			temp@49 {
52				label = "board";
53				compatible = "national,lm75";
54				reg = <0x49>;
55			};
56		};
57	};
58};
59
60&par_io {
61	/* UCC5 as HDLC controller for ICN */
62	pio_ucc5: ucc_pin@04 {
63		pio-map = <
64			/* port pin dir open_drain assignment has_irq */
65			2   0  1  0  2  0	/* TxD0 */
66			2   8  2  0  2  0	/* RxD0 */
67			2  29  2  0  2  0	/* CTS */
68			3  30  2  0  1  0	/* ICN CLK */
69			>;
70	};
71
72	/* UCC4 Piggy Ethernet */
73	pio_ucc4: ucc_pin@03 {
74		pio-map = <
75			/* port pin dir open_drain assignment has_irq */
76			3   4  3  0  2  0	/* MDIO */
77			3   5  1  0  2  0	/* MDC  */
78
79			1 18  1  0  1  0	/* TxD0 */
80			1 19  1  0  1  0	/* TxD1 */
81			1 22  2  0  1  0	/* RxD0 */
82			1 23  2  0  1  0	/* RxD1 */
83			1 26  2  0  1  0	/* RX_ER */
84			1 28  2  0  1  0	/* RX_DV */
85			1 30  1  0  1  0	/* TX_EN */
86			1 31  2  0  1  0	/* CRS */
87			3 10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
88		>;
89	};
90
91	pio_spi: spi_pin@01 {
92		pio-map = <
93			/* port pin dir open_drain assignment has_irq */
94			3  0  3  0  1  0 /* SPI_MOSI (PD0, bi, f3)  */
95			3  1  3  0  1  0 /* SPI_MISO (PD1, bi, f3)  */
96			3  2  3  0  1  0 /* SPI_CLK  (PD2, bi, f3)  */
97		>;
98	};
99};
100
101&localbus {
102	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
103		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
104		  2 0 0xa0000000 0x10000000>;   /* LB 2 LPXF */
105
106	flash@0,0 {
107		compatible = "cfi-flash";
108		reg = <0 0x00000000 0x04000000>;
109		bank-width = <2>;
110		#address-cells = <1>;
111		#size-cells = <1>;
112		partition@0 { /* 768KB */
113			label = "u-boot";
114			reg = <0 0xC0000>;
115		};
116		partition@c0000 { /* 128KB */
117			label = "env";
118			reg = <0xc0000 0x20000>;
119		};
120		partition@e0000 { /* 128KB */
121			label = "envred";
122			reg = <0xe0000 0x20000>;
123		};
124		partition@100000 { /* 64512KB */
125			label = "ubi0";
126			reg = <0x100000 0x3F00000>;
127		};
128	};
129};
130