1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P1020RDB-PC (36-bit address map) Device Tree Source
4 *
5 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
6 * Copyright 2019 NXP
7 */
8
9/include/ "p1020.dtsi"
10
11/ {
12	model = "fsl,P1020RDB-PC";
13	compatible = "fsl,P1020RDB-PC";
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&mpic>;
17
18	soc: soc@fffe00000 {
19		ranges = <0x0 0xf 0xffe00000 0x100000>;
20	};
21
22	pci1: pcie@fffe09000 {
23		reg = <0xf 0xffe09000 0x0 0x1000>;	/* registers */
24		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
25			  0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
26	};
27
28	pci0: pcie@fffe0a000 {
29		reg = <0xf 0xffe0a000 0x0 0x1000>;	/* registers */
30		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
31			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
32	};
33
34	aliases {
35		spi0 = &espi0;
36	};
37};
38
39/include/ "p1020rdb-pc.dtsi"
40/include/ "p1020-post.dtsi"
41
42&espi0 {
43	status = "okay";
44	flash@0 {
45		compatible = "jedec,spi-nor";
46		#address-cells = <1>;
47		#size-cells = <1>;
48		reg = <0>;
49		spi-max-frequency = <10000000>; /* input clock */
50	};
51};
52